AR# 9259: 3.1i Foundation ISE: Symbol generator does not preserve the case of the Verilog modules
3.1i Foundation ISE: Symbol generator does not preserve the case of the Verilog modules
Keywords: Symbol Generator, module, verilog, case preserve
General Description: When the "Create Schematic Symbol" process is run on a Verilog Module, the component names are generated as lower-case names. This can result in synthesis errors because the associated components will not be found.
Case sensitivity can be enforced by doing the following:
1- Open the schematic which contains the symbol. 2- Select Edit -> Symbol and click on the symbol. This will open the Symbol Editor. 3- Select Edit -> Attributes -> Symbol Attributes and click on the symbol. 4- In the Symbol Attributes dialog, select VeriModel and enter the case sensitive name and hit enter. 5- Save the symbol and exit.