We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9313

2.1i CORE Generator, C_IP5 - Dual port BlockRAM functional simulation model exhibits incorrect behavior


Keywords: CORE Generator, COREGen, dual, port, BlockRAM, functional, simulation, model, incorrect

Urgency: Standard

General Description:
The functional simulation model for the BlockRAM core exhibits incorrect behavior.

This is one of the incorrect behaviors:

- Address A and B equal
- Writes are done to port A
- Reads are form port B
- CLKA and CLKB have the same clock
- WEA goes high, and data is written to port A,

- Data out of port B is what has been written to port A
(This is incorrect; port B should be undefined instead.)


The correct behavior for the BlockRAM should be modified such that reading from and
writing to the same location at the same time will give an invalid data for read. This is
noted by page 5 of XAPP130 (http://support.xilinx.com/xapp/xapp130.pdf), under the
heading "Conflict Resolution."
AR# 9313
日期 09/05/2001
状态 Archive
Type 综合文章