General Description: The functional simulation model for the BlockRAM core exhibits incorrect behavior.
This is one of the incorrect behaviors:
When: - Address A and B equal - Writes are done to port A - Reads are form port B - CLKA and CLKB have the same clock - WEA goes high, and data is written to port A,
then: - Data out of port B is what has been written to port A (This is incorrect; port B should be undefined instead.)
The correct behavior for the BlockRAM should be modified such that reading from and writing to the same location at the same time will give an invalid data for read. This is noted by page 5 of XAPP130 (http://support.xilinx.com/xapp/xapp130.pdf), under the heading "Conflict Resolution."