Keyword: timing, TRCE, trace, timing
General Description:
When I perform an analysis on my design that includes a TIMEGRP period constraint, the synchronous paths from flip-flops to distributed RAM are not covered.
To work around this problem, use a NET PERIOD constraint.
This issue will be resolved in a future release of the software.
| AR# 9321 | |
|---|---|
| 日期 | 01/18/2010 |
| 状态 | Archive |
| Type | 综合文章 |