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AR# 9326

6.1i CORE Generator, ModelSim - "Warning: Component xxxxxx is not bound for a CORE Generator component"


Keywords: warning, component, not, bound, load, VSim, error

Urgency: Standard

General Description:
I am trying to functionally simulate a CORE Generator component in ModelSim, but the following warning is reported:

"Warning: Component xxxxxx is not bound for a CORE Generator component."

Will the simulation work?



Yes, the simulation will work. This warning expresses that it cannot find a VHDL file with an architecture of component "xxxxx" for the CORE Generator component.

This is handled by the configuration statement. Be sure to load the "Config" component (as opposed to "Architecture" or "Entity") when you start the simulation. For the simulation to work, you must simulate the CONFIGURATION. Not doing this is one of the most common sources of error.

If you use VHDL, the message regarding an unbound CORE Generator component will always be issued. This happens because, at the time of compilation, the simulator does not see a compiled component for the <coregen counter>, but the Configuration will bind this component to a pre-compiled model; therefore, one of the last things you should see in the MTI GUI when compiling the configuration LAST is something similar to:

# -- Loading entity c_mem_dp_block_v1_0

One of the last things you should see when loading the design using VSim is:

# Loading /group/techsup/data/mti/5.4a_2.1i_sp6/cgen_ip5/xilinxcorelib.c_mem_dp_block_v1_0(behavioral)

This has nothing to do with CORE Generator or MTI; it is simply the way VHDL works when it uses configuration declarations for binding.

If the counter is not working, examine the following:

1. Is the Configuration Declaration correct?
2. Are you simulating in the Config?
3. Is the library compiled correctly?

The most common cause of a CORE Generator component not working is a faulty Configuration Declaration, especially when the COREGen component is buried in a hierarchy.

If you are seeing these warnings regarding instantiated Xilinx components in the functional simulation, be sure that you declare the UniSim library in the VHDL code that contains the instantiation.


Another cause of this problem can be using an example file that uses a core that has not been installed yet. If this is the case, you must download the latest IP update and set it up in your simulator. Instructions on how to do this are available in the same location as the IP update.

The Xilinx IP Center is located at:
AR# 9326
日期 09/15/2003
状态 Active
Type 综合文章