General Description: Data is lost during burst transactions when the Xilinx core is supplying data.
This may be seen when a wait state is inserted dynamically by another agent during a burst transaction. The iwf_move or trf_unload signal will go inactive during a wait state, but the PCI_FIFO continues to read one more piece of data than necessary, effectively skipping a piece of data.
The pci_fifo module incorrectly enables the Block RAM modules.
At the bottom of the pci_fifo.v file, there are 3 Block RAM instantiations. The .EN port is assigned to logic high. This needs to be changed to the following: