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  3. AR# 9343: Virtex LogiCORE PCI32/33 - SB08 - Data is lost during read/write burst transactions when LogiCORE is supplying data.

AR# 9343

Virtex LogiCORE PCI32/33 - SB08 - Data is lost during read/write burst transactions when LogiCORE is supplying data.

描述

Keywords: DWORD, lost, pci, bridge, reference, FIFO, data, SB08, pci_fifo

Urgency: Standard

General Description:
Data is lost during burst transactions when the Xilinx core is supplying data.

This may be seen when a wait state is inserted dynamically by another
agent during a burst transaction. The iwf_move or trf_unload signal
will go inactive during a wait state, but the PCI_FIFO continues to read
one more piece of data than necessary, effectively skipping a piece of data.

解决方案

1

The pci_fifo module incorrectly enables the Block RAM modules.

At the bottom of the pci_fifo.v file, there are 3 Block RAM instantiations.
The .EN port is assigned to logic high. This needs to be changed to
the following:

///////////////////////////////////////////////////
// FILE: ./source/parts/generic/pci_fifo/pci_fifo.v

assign #TDEL ram_en = req_norm_wr | req_norm_rd;

RAMB4_S16 bit1500 (.WE(ram_we), .EN(ram_en), .RST(RESET), .CLK(CLK),
.ADDR({4'b0, ram_a}), .DI(DIN[15:0]), .DO(DOUT[15:0]));

RAMB4_S16 bit3116 (.WE(ram_we), .EN(ram_en), .RST(RESET), .CLK(CLK),
.ADDR({4'b0, ram_a}), .DI(DIN[31:16]), .DO(DOUT[31:16]));

RAMB4_S4 bit3532 (.WE(ram_we), .EN(ram_en), .RST(RESET), .CLK(CLK),
.ADDR({6'b0, ram_a}), .DI(DIN[35:32]), .DO(DOUT[35:32]));

2

An updated version of the pci_fifo.v file can be downloaded
from the Xilinx FTP site.

For PCs:
(Xilinx File http://www.xilinx.com/txpatches/pub/applications/pci/sb08_pci_fifo.zip)

For UNIX:
(Xilinx File http://www.xilinx.com/txpatches/pub/applications/pci/sb08_pci_fifo.tar.gz)
AR# 9343
日期 08/06/2001
状态 Archive
Type 综合文章