AR# 939: Foundation Simulator - Macro outputs are always "Z" during simulation.
Foundation Simulator - Macro outputs are always "Z" during simulation.
Keywords: Foundation, Simulator, Z, output
Problem Description: During simulation, the outputs of a user-created macro are always "Z" (schematic probes are yellow).
(NOTE: The following resolution applies only to version 1.17 of the simulator, which was shipped with Foundation 6.0.0.)
This can happen if the pin names on the macro symbol are written in lower-case. The simulation netlist will convert all net names to upper-case, but leave the symbol names in lower-case. The Foundation Logic Simulator is case-sensitive, so connectivity is lost between the symbol pins and the underlying net names.
While loading the simulation netlist, the following messages will appear in the Project Manager window:
SIM : Cannot find corresponding block pin for terminal A. Terminal will be changed to label SIM : NODE: A_IN SIM : No inputs in the node
Select the symbol and choose Options->Symbol Editor. Change the pin names to all upper-case letters.
This can happen if the macro symbol pins are defined as passive.
- Select the symbol and choose Options->Symbol Editor. (The pin descriptions appear in the lower left section of the Editor window.) - If any pin is of type PAS, select the pin. The pin name, direction, and shape are listed above the symbol graphic. - Use the pull-down menus to change the pin type to IN, OUT, or HIZ (for 3-state outputs).
(The following applies to Foundation F1.x Simulator)
If the macro is generated from VHDL or ABEL code, the port name (pin name) has a length limitation.
1. Bus name <= 9 characters long 2. Signal name <= 14 characters long
When the VHDL code has port names that exceed this length, the pin name in the macro will contain only 9 or 14 characters (i.e., busnametest: out STD_LOGIC_VECTOR (2 downto 0); in macro symbol, the pin name changes to busnamete[2:0]).
Since the pin name changes in the macro, the connectivity will be lost between the pin name and the underlying signal.
When loading simulation netlist, you will see the following message in the Project Manager window:
SIMUL: Cannot find corresponding block pin for terminal * Terminal will be changed to label..
To solve this problem, limit the length of the pin names in VHDL/ABEL code as specified above.
(The following applies only to Timing Simulations performed on back-annotated netlists for 3K devices):
NGD2EDIF, the utility which creates back-annotated netlists for timing simulation, may fail to connect signals in the netlist. This may be confirmed by viewing the time_sim.edn file.
To correct this problem, change the following Simulation Settings under "Implementation Options":
- Un-check "Correlate to Input Design." - Un-check the "Preserve Hierarchy" option.
The new netlist should wire the signals correctly.