AR# 9410


12.1 Timing Closure - Suggestions for high fanout signals


I placed a timing constraint on a path, but the constraint has errors. What can I do to make this timing constraint pass?


Possible suggestions for high fanout signals:
  • Floorplan or LOC the origin and the global buffer of the high fanout signal.
  • Duplicate the driver and tell the synthesis tool not to remove the duplicate logic.
  • Use specific net fanout control on the specific net, if the synthesis tool allows.

For additional suggestions and recommendations, see the following Answer Records:
AR# 9410
日期 12/15/2012
状态 Active
Type 综合文章
Tools More Less
People Also Viewed