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AR# 9413

12.1 Timing Closure - Suggestions for I/O 3-state enable paths

Description

I placed a timing constraint on a path, but the constraint has errors. What can I do to make this timing constraint pass?

解决方案

You can use 3-state flip-flops in the IOB; you must have separate flip-flops for each IOB. To place the flip-flop in the IOB, you can use the "IOB=TRUE" constraint in the UCF.

UCF example

INST flip_flop1 IOB=TRUE;

For additional suggestions and recommendations, see the following Answer Records:

- Suggestions for avoiding high fan-out signals, see (Xilinx Answer 9410).

- Suggestions for state machine optimization, see (Xilinx Answer 9411).

- Suggestions for long carry logic chains, see (Xilinx Answer 9412).

- Suggestion for paths through TBUFs, see (Xilinx Answer 9414).

- Suggestions for timing through irrelevant paths such as RESET or ".SR" pin, see (Xilinx Answer 9415).

- Suggestions for using multi-cycle paths, such as a path through a ".CE" pin, see (Xilinx Answer 9416).

- Suggestions for how to avoid having too many levels of logic, see (Xilinx Answer 9417).

- Suggestions for timing constraints that miss their goals by 5% to 10%, see (Xilinx Answer 9418).

- Suggestions for timing constraints that miss their goals by 10% to 15%, see (Xilinx Answer 9419).

AR# 9413
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
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