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AR# 9415

12.1 Timing Closure - Suggestions for timing through irrelevant paths such as RESET or ".SR" pin


I placed a timing constraint on a path, but the constraint has errors. How can I make this timing constraint pass?


These paths can be Timing Ignored (TIG), either by paths or by net. The following syntax is for NET and PATH TIG: (Comments = #)
#Net TIG;
NET reset_net TIG;
#Path TIG;
TIMESPEC TS_TIG = FROM source_group TO destination_group TIG;
For additional suggestions and recommendations, see the following Answer Records:
- Suggestions for avoiding high fanout signals, see (Xilinx Answer 9410).
- Suggestions for state machine optimization, see (Xilinx Answer 9411).
- Suggestions for long carry logic chains, see (Xilinx Answer 9412).
- Suggestions for I/Os 3-state enable paths, see (Xilinx Answer 9413).
- Suggestion for paths through TBUFs, see (Xilinx Answer 9414).
- Suggestions for using multi-cycle paths, such as a path through a ".CE" pin, see (Xilinx Answer 9416).
- Suggestions for how to avoid having too many levels of logic, see (Xilinx Answer 9417).
- Suggestions for timing constraints that miss their goals by 5% to 10%, see (Xilinx Answer 9418).
- Suggestions for timing constraints that miss their goals by 10% to 15%, see (Xilinx Answer 9419).
AR# 9415
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章
  • ISE - 10.1
  • ISE Design Suite - 11.1
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