UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 9417

12.1 Timing Closure - Suggestions for how to avoid having too many levels of logic

Description


I placed a timing constraint on a path, but the constraint has errors and too many levels of logic.
How can I make this timing constraint pass?

解决方案


This is a case where logic exceeds some percentage of the total path delay, implying that there is too much logic between timing end points; the amount of logic must be reduced in order to meet timing requirements.
This number was traditionally around 50% for older architectures; it would need to be quantified for Virtex families (60%). There are exceptions to this rule for carry chain paths, in which the logic delays are much smaller and would allow for a higher number of logic levels or a lower component percentage.
To reduce the levels of logic, return to the source and try the following:
  1. Issue State Machine Optimization Suggestions, see (Xilinx Answer 9411)
  2. Use CASE statements instead of nested IF-ELSE statements.
  3. Use 3-state instead of large muxes (7 or more inputs).
  4. Use creative math; shift instead of multiplying by multiples of two.
  5. Use decoders instead of comparators.
  6. Balance logic around registers.
  7. Pyramid logic with parentheses instead of serial implementation.
  8. Use IF-THEN-ELSE statements only to do the following:
    • Pre-decode and register counter values.
    • Add a level of pipelining to pre-decode and register input signals.
  9. Use muxes with more than 7-bit wide buses only to do the following:
    • Instead of logic, use registers that are in a 3-state condition.
    • Drive enable signals from registers; 3-states are in a 3-state condition when enable signals are "1," and drive signals when the enable is "0".
    • Use floorplan 3-states.
  10. Add pipeline registers.

For additional suggestions and recommendations, see the following Answer Records:
AR# 9417
创建日期 08/21/2007
Last Updated 03/07/2013
状态 Active
Type 综合文章
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • Less