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AR# 9418

14.x Timing Closure - Suggestions on how to avoid the timing constraint missing the goal by 5% to 10%

Description

I placed a timing constraint on a path, but the constraint has errors and misses the goal by 5% to 10%. What can I do to make this timing constraint pass?

解决方案


If your constraint misses its timing requirement by 5% to 10%, and the logic delay is less than 60%, you can try selecting a higher placement effort (4 or 5) and constraining the I/Os, especially data buses.

For additional suggestions and recommendations, see the following Answer Records:
- Suggestions for avoiding high fanout signals, see (Xilinx Answer 9410).
- Suggestions for state machine optimization, see (Xilinx Answer 9411).
- Suggestions for long carry logic chains, see (Xilinx Answer 9412).
- Suggestions for I/Os 3-state enable paths, see (Xilinx Answer 9413).
- Suggestions for paths through TBUFs, see (Xilinx Answer 9414).
- Suggestions for timing through irrelevant paths such as RESET or ".SR" pin, see (Xilinx Answer 9415).
- Suggestions for using multi-cycle paths, such as a path through a ".CE" pin, see (Xilinx Answer 9416).
- Suggestions for how to avoid having too many levels of logic, see (Xilinx Answer 9417).
- Suggestions for timing constraints that miss their goals by 10% to 15%, see (Xilinx Answer 9419).
AR# 9418
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • Less