General Description: When probing the input of a global clock and its feedback pin on a clock DLL, a discrepancy of over .3 ns has been seen between the two clock signals.
解决方案
There is a problem in the Virtex-E BitGen equations. BitGen determined that if a signal went from the DLLFB pin of a DLLIOB directly to the CLKFB pin of a DLL, the DLL feedback connection was "on-chip" instead of "off-chip". This created an improper clock de-skew of approximately 250 ps.