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AR# 9438

3.1i XST - XST does not see Verilog meta comments in files originating from `include statements.


Keywords: XST, meta, comments, Verilog, Synplicity, Synplify, attribute, passing, 3,1i, include

Urgency: Standard

General Description:
When I use meta comments in files that are brought into a project via a TCL-based `include statement, the meta comments are ignored without any error or warning being reported.

For example, a file design.v has `include "C:/main_mod.v" (note that there is a "/' instead of an MS-DOS-based '\"), where main_mod.v has a meta comment similar to <// synthesis attribute keep of tmp is true>. The meta comment will be ignored.


This problem is fixed in the latest 3.1i Service Pack, available at:
The first service pack containing the fix is 3.1i Service Pack 6.
AR# 9438
日期 08/20/2002
状态 Archive
Type 综合文章