UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 945

5.20 3000A PPR - Support for dual phase clocks in 3000A devices

Description

Dual phase clocking is supported by PPR 5.0 and later
for XC3000A devices, but not by APR for XC3000 devices.
It is highly recommended that the clock signal in this
situation be sourced by the ACLK buffer.
Using GCLK is not an option because it cannot connect
to both of the clock lines on an XC3000/XC3000A die edge.
If no clock buffer is used, you risk introducing skew
between the two phases of the clock.

Currently the only known problem with PPR in this
context is that, as of 11/6/95, PPR 5.2.0 does not
understand that a single clock line can drive
EITHER:

1. INLATs with INVERTED G pins and OUTFF(T)/INFFs with
NON-INVERTED C pins

**OR**

2. INLATs with NON-INVERTED G pins and OUTFF(T)/INFFs
with INVERTED C pins

解决方案

Solutions 261 and 958 document how you can implement
dual phase clocks in an XC3000 device (APR won't do it for
you automatically).
AR# 945
创建日期 08/31/2007
Last Updated 04/10/2000
状态 Archive
Type ??????