AR# 9478

3.1i Virtex MAP - Pack error: WRT shared FLUT pins between LUT4 and MULTAND.

描述

Keywords: MULTAND, LUT, Pack, ERROR:Pack:679, unable, obey, constraints

Urgency: Standard

General Description:
A case has been seen where MAP rejects a pack involving a LUT4 and MULTAND
with shared signals. One of the shared signals is a GND net. The following error occurs:

ERROR:Pack:679 - Unable to obey design constraints (MACRONAME =
Counter_block/PhyPktCntrCore/hset, RLOC = R6C0.S1) which require the
combination of the following symbols into a single slice component:
XORCY symbol "Counter_block/PhyPktCntrCore/BU100" (Output Signal =
Counter_block/PhyPktCntrCore/N109)
FLOP symbol "Counter_block/PhyPktCntrCore/BU101" (Output Signal =
Counter_block/PhyPktCntr<19>)
LUT symbol "Counter_block/PhyPktCntrCore/BU92" (Output Signal =
Counter_block/PhyPktCntrCore/N713)
MULTAND symbol "Counter_block/PhyPktCntrCore/BU93" (Output Signal =
Counter_block/PhyPktCntrCore/N727)
MUXCY symbol "Counter_block/PhyPktCntrCore/BU94" (Output Signal =
Counter_block/PhyPktCntrCore/N729)
XORCY symbol "Counter_block/PhyPktCntrCore/BU95" (Output Signal =
Counter_block/PhyPktCntrCore/N108)
FLOP symbol "Counter_block/PhyPktCntrCore/BU96" (Output Signal =
Counter_block/PhyPktCntr<18>)
LUT symbol "Counter_block/PhyPktCntrCore/BU97" (Output Signal =
Counter_block/PhyPktCntrCore/N745)
MULTAND symbol "Counter_block/PhyPktCntrCore/BU98" (Output Signal =
Counter_block/PhyPktCntrCore/N759)
MUXCY symbol "Counter_block/PhyPktCntrCore/BU99" (Output Signal =
Counter_block/PhyPktCntrCore/N761)
The function generator Counter_block/PhyPktCntrCore/BU92 is unable to be
placed in the F position because there is a conflict for the F function
generator input pins.

解决方案

This error is due to a bug in constant pushing that makes the LUT connectivity
incompatible with the MULTAND.

This is fixed in the first major release following version 3.1i, currently scheduled for
July, 2001.
AR# 9478
日期 08/19/2002
状态 Archive
Type 综合文章