We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AR# 9484

3.1i 4KXL PAR - Guided PAR fails with "Error: Place:489 The clock group consisting of the following components..."


Keywords: Place, 489, PAR, guide

Urgency: Standard

General Description:
PAR is unable to guide some 4KXL designs and fails with the following error, even though there are no prohibits in the PCF file:

ERROR:Place:489 - The clock group consisting of the following components is impossible to legally place, as all of the site sets that could hold this configuration contain a prohibited site that this group requires. Please consult the Xilinx Programmable Logic Data Book for more information on clock buffers.



This problem can occur with leverage guide designs for 4000XL, XLA, XV, and Spartan-XL (any architecture that contains BUFG/BUFGLS/BUFGE triples).

The problem occurs because of a route-through between the CLKIO and the buffer it drives. This problem only happens if the CLKIO is locked to the site in the PCF file and the global buffer it drives is not locked.

Therefore, the work-around is to either lock (or not lock) both the CLKIO and its associated buffer. This constraint can be placed in the UCF.


This problem is fixed in the latest 3.1i Service Pack, available at:
The first service pack containing the fix is 3.1i Service Pack 3.
AR# 9484
日期 10/21/2008
状态 Archive
Type 综合文章