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AR# 9559

3.1i CORE Generator Virtex - When generating Single-Port Block Memory v1_0 from the GUI, the falling_edge clock polarity is ignored.


Urgency: Hot

General Description:

When generating the Single-Port Block Memory using CORE Generator 3.1i, setting the Clock option to "Falling Edge" from the Single-Port Block Memory GUI does not work. The resulting EDIF netlist will actually have "Rising Edge" polarity, and even the generated .xco file will specifically say that it is using "Rising Edge" for the clock.


The work-around is to manually edit the .xco file and change the value of the "Clock_On" parameter to "Falling Edge":

CSET clock_on = Falling_Edge

Then, regenerate the Single-Port Block Memory using the modified .xco file.

1. Open the main CORE Generator GUI.

2. Select File -> Execute Command File.

3. Select the .xco file you have just modified.

4. Click "OK."

5. Click "OK to Overwrite Files."

This will give you a new EDIF netlist with a "Falling Edge" polarity clock.

This problem exists for the Single-Port Block Memory v1_0, which was delivered in the following software and IP updates:

2.1i w/ C_IP5


3.1i w/ D_IP1

The new Block Memory Cores v3_0 that were delivered with 3.1i IP Update #2 (D_IP2) no longer support falling-edge clocks. In addition, the feature that allows you to specify Active High/Low for RSTA, RSTB, WEA, WEB, ENA and ENB is no longer supported.

This applies to both Single-Port and Dual-Port Block Memories in v3_0. If the inversion is needed for any of these signals, the inverter can be applied to the signal outside of the core, and the mapper should properly absorb the inverter into either the register (for registered inputs) or the Block Memory.

AR# 9559
日期 06/04/2010
状态 Archive
Type 综合文章