How long must a reset be applied to a DLL in order to reset it?
A reset needs to be asserted for approximately only 2 ns.
Approximately four clock cycles are needed for the delayed clocks to be flushed out of the DLL.
When CLKDLL is configured with external feedback, a RESET after configuration is recommended. Please see (Xilinx Answer 14425) for more information.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 41530 | Xilinx Obsolete Device Solution Center - Clocking for devices covered by XCN12026 | N/A | N/A |
| 37214 | Virtex-6 FPGA Design Assistant - Troubleshoot common block RAM/FIFO problems | N/A | N/A |
| AR# 9586 | |
|---|---|
| 日期 | 05/14/2014 |
| 状态 | Archive |
| Type | 综合文章 |