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AR# 9588

3.1i Virtex PAR - Range constraint expansion in Modular Design uses too much memory.

Description

Keywords: Modular, par, place, placer, range, memory

Urgency: Standard

Problem Description:
Currently range constraints are put in the pcf as:

COMP X LOCATE=SITE A:B

The desprefs code expands this such that a constraint is put
onto each site A:B that says it can hold comp X. This eats up
a lot of memory when working with modules on large designs.

A fix is being developed that is more efficient in memory usage.

解决方案

This change is available in the latest 3.1i Service Pack available at:
http://support.xilinx.com/support/techsup/sw_updates/

AR# 9588
创建日期 09/01/2007
Last Updated 10/21/2008
状态 Archive
Type 综合文章