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AR# 9603

3.1i Virtex PAR - Designs with a large number of SRL16s may see poor PAR performance.

Description

Keywords: PAR, SRL16, PWR, VCC, GND, time, XIL_MAP_NOSHIFTONES

Urgency: Standard

General Description:
Currently, MAP generates a GLOBAL_LOGIC1 and GLOBAL_LOGIC0 signal to drive constants onto the F an G inputs of LUT RAM that are used in the SRL library element. The extreme number of VCC loads that can occur in such designs will often lead to excessive router run time, as well as poor circuit performance due to route congestion.

解决方案

The solution is to rely on a power-up state of "1" for these address pins, and not to consume general routing to accomplish the same task. An environment variable has been added to MAP so that it will simply remove the SRL16 LUT RAM address pins tied to VCC from the VCC net:

For PCs:
set XIL_MAP_NOSHIFTONES=1

For Workstations:
setenv XIL_MAP_NOSHIFTONES 1

The design must be re-mapped after the variable has been set.
AR# 9603
创建日期 08/31/2007
Last Updated 10/21/2008
状态 Archive
Type 综合文章