General Description: When instantiating a Xilinx primitive in FPGA Express (VHDL or Verilog), I encounter the following error message:
Positional binding is not allowed when linking the cell '...' to the target primitive design '...' FPGA-LINK-19
The "binding" to which this message refers is the way in which ports in your instance are associated with ports in the component declaration (VHDL) or module declaration (Verilog). "Positional binding" means that ports are associated by the order in which they appear in the port list. In this case, FPGA Express wants named-based binding, rather than positional binding.
Please note the following examples:
Verilog ---------------- module GCLK ( O, I ); output O; input I; endmodule
positional binding (ports associated by order of appearance): GCLK my_clk (my_output, my_input); // correct GCLK my_clk (my_input, my_output); // incorrect