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AR# 9690

Virtex/-E/-II, Spartan-II - Which CLKDLL/DCM outputs can drive the feedback input of a CLKDLL/DCM?


General Description:

When using an internal feedback path, which output of the DLL/DCM should I use as a feedback to CLKFB?


The CLKDLL/DCM can use either the CLK2X output or the CLK0 phase output as the CLKFB feedback input. The rising edges of the feedback input must correspond to the CLKIN input on the DLL. For more information on CLKDLL for Virtex and Virtex-E devices, see the Xilinx Application Note (Xilinx XAPP132): "Using the Virtex Delay-Locked Loop." Additionally, the data sheets contain helpful information:

For Virtex devices, see the Detailed Functional description data sheet: Architecture Description -> Programmable Routing Matrix -> Delay-Locked Loops at:


For Virtex-E devices, see the Detailed Functional description data sheet: Architecture Description -> Global Clock Distribution -> Digital Delay Locked Loops at:


For more information on DCM, see the appropriate user guide at:


1. Select the "Virtex-II Platform FPGA User Guide" or the "Virtex-II Pro Platform FPGA User Guide."

2. Select Design Considerations -> Digital Clock Managers (DCMs).

AR# 9690
日期 12/15/2012
状态 Active
Type 综合文章