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AR# 9752

3.x FPGA Express - Library logical name XILINXCORELIB is not mapped to a host directory. (VSS-1071) (FPGA-dm-hdlc-unknown)

Description

Keywords: XilinxCoreLib, map, library, VSS, 1071, CORE Generator, Coregen

Urgency: Standard

General Description:
FPGA Express gives the following error message when trying to simulate a core:

Synopsys FPGA Express 3.x: Library logical name XILINXCORELIB is not mapped to
a host directory. (VSS-1071) (FPGA-dm-hdlc-unknown)

解决方案

This is caused by the absence of the following lines from the CORE Generator .vho
file before and after the XilinxCoreLib library declaration:

-- synopsys translate_off
-- synopsys translate_on

These statements tell Synopsys to ignore this library. The XilinxCoreLib is used for
simulation only, not for synthesis.
AR# 9752
创建日期 07/20/2000
Last Updated 08/11/2003
状态 Archive
Type 综合文章