The HSTL (High-Speed Transceiver Logic) I/O standard, which consists of four separate classes, typically operates at 1.5V. Alternatively, it is often operated at 1.8V.
Do Xilinx devices support 1.8V HSTL operation?
Xilinx support for 1.8V HSTL is outlined in the following white paper:
Please refer to the Xilinx Libraries Guide for information about available software primitives for 1.5V and 1.8V HSTL buffers (only Virtex-II offers separate primitives):
Both 1.5V and 1.8V HSTL can be modeled using the HSTL1, HSTL2, HSTL3, and HSTL4 IBIS models (only Virtex-II supports HSTL2). The models are available for download at:
SPICE models are available for download at:
For more information about the HSTL standard, please see the standard specification at: