AR# 9774

VSS : How do I simulate Xilinx designs in VSS? (VHDL)


Synopsys, VSS, vhdlan, vhdlsim, simulation, how

Urgency: Standard

General Description:

How do I simulate Xilinx designs
in Synopsys VSS?



VSS requires a WORK directory to put
the compiled data in. First, create
the WORK directory in the project
directory as follows:

mkdir WORK

Make sure the following line is
added to the .synopsys_vss.setup

WORK: /path_to_directory/WORK

Run the following command to
compile the files:
vhdlan -i file1.vhd file2.vhd
vhdlan -i testbench.vhd

The following command will
load the simulation:
vhdlsim -e commandfile.txt cfg_tstbench

where commandfile.txt contains the commands
to start up the waveform viewer, add signals
and stimulus. For more information on the
commandfile.txt, consult Synopsys VSS


For information on how to compile Xilinx libraries for
VSS, see solution 9755 at
AR# 9774
日期 10/01/2008
状态 Archive
Type 综合文章