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AR# 9786

3.1i Virtex-II, CORE Generator - The .asy file for a Block Memory (single-port) is not generated correctly

Description

Keywords: Virtex-II, block, memory, Asynchronous, FIFO, ASY, symbol file

Urgency: Standard

General Description:
When I generate a Block Memory Single Port (Virtex-II) in CORE Generator, only a portion of the .asy file is produced. The pin information is not entered into the .asy file, even though the template .asy file for the core is available.

(An example .xco and .asy have been copied to the bug cases directory. This problem is also seen with Asynchronous FIFO, and perhaps with other cores as well.)

解决方案

This problem was fixed in 3.1i_IP_Update #2, which was released in November, 2000.

This update is available at:
http://www.xilinx.com/ipcenter/coregen/updates.htm
AR# 9786
创建日期 07/25/2000
Last Updated 08/23/2002
状态 Archive
Type 综合文章