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3.1i XST - ERROR: (VLG__5002). <path>\<file_name> Line ##. Continuous assignment lval '<bus_name>' not a net
Keywords: Verilog, continuous, bus, bit, bit-wise, wise
The Verilog construct:
assign net_name = & ~bus_name;
may produce the following error if you try to perform a bit-wise operation on a negated bus:
ERROR: (VLG__5002). <path>\<file_name> Line ##. Continuous assignment lval '<bus_name>' not a net
The above Verilog construct is legal.
To work around the problem, add parentheses around the bus name (including the negation operator).
assign net_name = & (~bus_name);
NOTE: This problem is fixed in the 4.1i software release.