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AR# 9849

3.4 FPGA Express - How do I use the LVDS/LVPECL IOSTANDARD in FPGA Express?

Description


Urgency: Standard



General Description:

FPGA Express does not recognize IBUF_LVDS, IBUF_LVPECL, OBUF_LVDS,

OBUF_LVPECL, IOBUF_LVDS and IOBUF_LVPECL as valid primitves. If I

try to instantiate the LVDS buffers, FPGA Express will insert I/O buffers, causing

errors when the design is run through the implementation tools.



See (Xilinx Solution 8202) for more options.

解决方案


VHDL:



There are many approaches to the problem of getting the LVDS standard in your

design and in the proper location. Below is just one solution (in VHDL) that shows

a flip-flop using the LVDS standard on the input and output. The pin location

constraints correspond to a Virtex-E CS144 package. For more information on

using the LVDS standard in your design, please see the LVDS design guide in the

Virtex-E data sheet at http://support.xilinx.com/partinfo/ds022.pdf


(If you want the LVPECL standard, change "LVDS" to "LPECL.")



library IEEE;

use IEEE.std_logic_1164.all;



entity flip_flop is

port(d: in std_logic;

clk : in std_logic;

q : out std_logic;

q_n : out std_logic);

end flip_flop;



architecture flip_flop_arch of flip_flop is



component IBUF

port(I: in std_logic;

O: out std_logic);

end component;



component OBUF

port(I: in std_logic;

O: out std_logic);

end component;



attribute IOSTANDARD : string;

attribute LOC : string;



attribute IOSTANDARD of u1 : label is "LVDS";

attribute IOSTANDARD of u2 : label is "LVDS";

attribute IOSTANDARD of u3 : label is "LVDS";



----------------------------------------------------------------------------------------------

-- Pin location A5 on the CS144 package represents the 'positive' LVDS pin.

-- Pin location D8 represents the 'positive' LVDS pin.

-- Pin location C8 represents the 'negative' LVDS pin.

----------------------------------------------------------------------------------------------



attribute LOC of u1 : label is "A5";

attribute LOC of u2 : label is "D8";

attribute LOC of u3 : label is "C8";



signal d_lvds, q_lvds, q_lvds_n : std_logic;



begin



u1: IBUF port map (d,d_lvds);

u2: OBUF port map (q_lvds,q);

u3: OBUF port map (q_lvds_n,q_n);



process (clk) begin

if clk'event and clk = '1' then

q_lvds <= d_lvds;

end if;

end process;



q_lvds_n <= not(q_lvds);



end flip_flop_arch;



Verilog:



There are many approaches to the problem of getting the LVDS standard in your

design and in the proper location. Below is just one solution (in Verilog) that shows

a flip-flop using the LVDS standard on the input and output. The pin location

constraints correspond to a Virtex-E CS144 package. For more information on using

the LVDS standard in your design, please see the LVDS design guide in the Virtex-E

data sheet at http://support.xilinx.com/partinfo/ds022.pdf


(If you want the LVPECL standard, change "LVDS" to "LPECL.")



module flip_flop (d, clk, q, q_n);



*******************************************************************************

Pin location A5 on the CS144 package represents the 'positive' LVDS pin.

Pin location D8 represents the 'positive' LVDS pin.

Pin location C8 represents the 'negative' LVDS pin.

*******************************************************************************



input d;

//synopsys attribute LOC "A5"



input clk;



output q;

//synopsys attribute LOC "D8"



output q_n;

//synopsys attribute LOC "C8"



wire d,clk,d_lvds,q;



reg q_lvds;



IBUF u1 (.I(d), .O(d_lvds));

//synopsys attribute IOSTANDARD "LVDS"



OBUF u2 (.I(q_lvds), .O(q));

//synopsys attribute IOSTANDARD "LVDS"



OBUF u3 (.I(q_lvds_n), .O(q_n));

//synopsys attribute IOSTANDARD "LVDS"



always @(posedge clk) q_lvds=d_lvds;



assign q_lvds_n=~q_lvds;



endmodule



UCF:



The following example represents UCF syntax using the port names from the two

examples above. If using the UCF syntax, there is no need to pass the

IOSTANDARD and LOC attributes through your HDL. For more information on

using the LVDS standard in your design, please see the LVDS design guide in the

Virtex-E data sheet at http://support.xilinx.com/partinfo/ds022.pdf


(If you want the LVPECL standard, change "LVDS" to "LPECL.")



NET "d" LOC = A5; #positive LVDS location

NET "q" LOC = D8; #positive LVDS location

NET "q_n" LOC = C8; #negative LVDS location



NET "d" IOSTANDARD = LVDS;

NET "q" IOSTANDARD = LVDS;

NET "q_n" IOSTANDARD = LVDS;
AR# 9849
创建日期 08/31/2007
Last Updated 07/23/2011
状态 Archive
Type 综合文章