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AR# 9920

4.2i Foundation - An error reports: "ABORT @ ###"

Description

Keywords: ABORT, Synopsys, @, Aldec, FPGA Express

Urgency: Standard

General Description:
When I synthesize VHDL or Verilog in Foundation, the following error message is reported:

"Abort @ ###"

解决方案

This error can be caused by the interface between FPGA Express and Foundation. Determine the true source of the problem by following these steps:

1. Open the design in the stand-alone mode of FPGA Express and synthesize the design. Is the "abort" message reported?

No: An issue with communication exists. Please open a WebCase with Xilinx Customer Service at:
http://support.xilinx.com/support/clearexpress/websupport.htm

Yes: Proceed as directed below.

2. Synthesize the modules one at a time to determine which module is causing the error.

3. Once you have located the module, comment out sections of code until the offending line is found. If the code is correct but is being interpreted incorrectly, please open a WebCase with Xilinx Customer Service at:
http://support.xilinx.com/support/clearexpress/websupport.htm
AR# 9920
创建日期 08/14/2000
Last Updated 08/12/2003
状态 Archive
Type 综合文章