AR# 9973: 3.1i Virtex MAP - MAP incorrectly optimizes MUXCYs and XORCYs into LUTs, leading to pack errors.
AR# 9973
3.1i Virtex MAP - MAP incorrectly optimizes MUXCYs and XORCYs into LUTs, leading to pack errors.
Description
Keywords: 3.1i MAP, pack:679, Virtex, LUT
Urgency: Standard
General Description: Cases have been seen where RLOC'dMUXCYs and XORCYs are being reduced to buffers due to mapping optimization, but are then being incorrectly treated as RLOC'd LUT components.
This results in packing errors where MAP complains that "there are more than two function generators" due to conflicts with the real LUTs. The following error appears:
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME = core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/div/a1/top_cont, RLOC = R33C22.S0) which require the combination of the following symbols into a single slice component:LUT symbol core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/BU5980" (Output Signal = core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/N117890) LUT symbol "core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/BU 5981" (Output Signal = core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/N117945) FLOP symbol "core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/BU5982" (Output Signal = core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/N23740) LUT symbol "core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/BU5983" (Output Signal = core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/N118299) LUT symbol "core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/BU5984" (Output Signal = core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/N117889) LUT symbol "core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/BU5985" (Output Signal = core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/N117944) FLOP symbol "core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/BU5986" (Output Signal = core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/N23739) LUT symbol "core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/BU5979" (Output Signal = core_notri/proc_notri/c_norm_pipeline_c_div_result_scale/N118253) There are more than two function generators. Please correct the design constraints accordingly.
NOTE: Please see (Xilinx Solution 9597) for a similar case that is to be fixed in Service Pack 8.
2
A workaround is to override the XORCY RLOC with the following UCF attribute:
INST U1/U1/BU2 USE_RLOC=FALSE ;
Ideally, the RLOC should only be overridden for the symbols that are not really LUT symbols. In some cases, it is too difficult to do this. An alternative is to override the RLOC for every LUT symbol mentioned in the error.