UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Memory Interfaces Design Hub - UltraScale DDR3/DDR4 Memory

This page covers Memory Interfacing in UltraScale Devices using the Memory Interface Generator (MIG) in the Vivado Design Suite

IntroductionDate
 Memory Interface UltraScale Design Checklist 
 UltraScale Architecture FPGAs Memory IP Product Guide05/22/2019
 Creating a Memory Interface Design using Vivado MIG05/22/2019
 Designing with UltraScale Memory IP09/16/2014
 Memory Interface UltraScale IP Release Notes05/29/2019
 Supported Memory Interfaces and Data Rates 
Design RequirementsDate
 Input Clock Guidelines05/22/2019
 Memory Interface External Clocking03/15/2016
 PCB Guidelines for DDR4 SDRAM06/26/2019
 PCB Guidelines for DDR3 SDRAM06/26/2019
 DDR4 Pin Rules05/22/2019
 DDR3 Pin Rules05/22/2019
 I/O Planning for UltraScale Device Memory IP05/22/2019
 Designing for High Efficiency05/22/2019
 Calculating User Specified Pattern Efficiency Using the Memory IP Performance Testbench05/22/2019
 Designing with UltraScale Memory IP09/16/2014
 Importing I/O Ports for an Existing Pin-Out/Board05/22/2019
Interfacing to Memory Interface IPDate
 Interfacing to the Memory IP User Interface05/22/2019
 Interfacing to the PHY Only Interface05/22/2019
 Interfacing to the AXI4 Slave Interface05/22/2019
Simulating Memory Interface IPDate
 Simulating the Memory IP Example Design05/22/2019
 Vivado Logic Simulation Design Hub06/27/2019
Frequently Asked Questions (FAQ)Date
 Memory IP UltraScale Solution Center - Frequently Asked Questions (FAQ) 

Additional Learning Materials

Additional Learning Materials

的页面