Performance and Resource Utilization for RAM-based Shift Register v12.0

Vivado Design Suite Release 2019.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_fl_128 Fixed_Length 16 128 CLK 636 64 32 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_fl_512 Fixed_Length 16 512 CLK 636 256 80 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_fl_64 Fixed_Length 16 64 CLK 636 32 32 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_vl_128 Variable_Length_Lossless 16 128 CLK 533 64 16 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_vl_512 Variable_Length_Lossless 16 512 CLK 325 272 16 0 0 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_vl_64 Variable_Length_Lossless 16 64 CLK 636 32 16 0 0 0 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_fl_128 Fixed_Length 16 128 CLK 735 64 32 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_fl_512 Fixed_Length 16 512 CLK 735 256 48 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_fl_64 Fixed_Length 16 64 CLK 735 32 32 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_vl_128 Variable_Length_Lossless 16 128 CLK 735 64 16 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_vl_512 Variable_Length_Lossless 16 512 CLK 494 272 16 0 0 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_vl_64 Variable_Length_Lossless 16 64 CLK 735 32 16 0 0 0 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_fl_128 Fixed_Length 16 128 CLK 872 64 32 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_fl_512 Fixed_Length 16 512 CLK 872 256 48 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_fl_64 Fixed_Length 16 64 CLK 872 32 32 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_vl_128 Variable_Length_Lossless 16 128 CLK 872 64 16 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_vl_512 Variable_Length_Lossless 16 512 CLK 713 272 16 0 0 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_vl_64 Variable_Length_Lossless 16 64 CLK 872 32 16 0 0 0 PRODUCTION 1.23 03-18-2019

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_fl_128 Fixed_Length 16 128 CLK 636 64 32 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_fl_512 Fixed_Length 16 512 CLK 636 256 80 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_fl_64 Fixed_Length 16 64 CLK 636 32 32 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_vl_128 Variable_Length_Lossless 16 128 CLK 533 64 16 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_vl_512 Variable_Length_Lossless 16 512 CLK 341 272 16 0 0 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_vl_64 Variable_Length_Lossless 16 64 CLK 636 32 16 0 0 0 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_fl_128 Fixed_Length 16 128 CLK 735 64 32 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_fl_512 Fixed_Length 16 512 CLK 735 256 48 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_fl_64 Fixed_Length 16 64 CLK 735 32 32 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_vl_128 Variable_Length_Lossless 16 128 CLK 669 64 16 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_vl_512 Variable_Length_Lossless 16 512 CLK 494 272 16 0 0 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_vl_64 Variable_Length_Lossless 16 64 CLK 735 32 16 0 0 0 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_fl_128 Fixed_Length 16 128 CLK 872 64 32 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_fl_512 Fixed_Length 16 512 CLK 872 256 48 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_fl_64 Fixed_Length 16 64 CLK 872 32 32 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_vl_128 Variable_Length_Lossless 16 128 CLK 872 64 16 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_vl_512 Variable_Length_Lossless 16 512 CLK 680 272 16 0 0 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_vl_64 Variable_Length_Lossless 16 64 CLK 872 32 16 0 0 0 PRODUCTION 1.23 03-18-2019

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
ShiftRegType
Width
Depth
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_fl_128 Fixed_Length 16 128 CLK 872 64 32 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_fl_512 Fixed_Length 16 512 CLK 872 256 48 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_fl_64 Fixed_Length 16 64 CLK 872 32 32 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_vl_128 Variable_Length_Lossless 16 128 CLK 872 64 16 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_vl_512 Variable_Length_Lossless 16 512 CLK 691 272 16 0 0 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_vl_64 Variable_Length_Lossless 16 64 CLK 872 32 16 0 0 0 PRODUCTION 1.25 05-09-2019

COPYRIGHT

Copyright 2019 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners.

LEGAL INFORMATION: PLEASE READ

The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of Xilinx's limited warranty, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications, please refer to Xilinx's Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos.