Performance and Resource Utilization for DDS Compiler v6.0

Vivado Design Suite Release 2019.1

Interpreting the results

This page contains maximum frequency and resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Kintex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7k480t ffg901 -1 k7_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 456 110 242 2 4 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 456 253 399 0 4 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 456 168 244 0 2 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 456 26 61 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 40 170 3 1 0 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 456 88 372 5 1 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 65 144 0 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 40 146 3 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 456 32 194 4 0 1 PRODUCTION 1.12 2017-02-17
xc7k480t ffg901 -1 k7_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 456 91 215 4 0 1 PRODUCTION 1.12 2017-02-17

Kintex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku115 flva1517 -1 ku_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 522 103 242 2 4 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 522 241 399 0 4 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 522 170 244 0 2 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 522 26 61 0 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 40 170 3 1 0 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 522 93 372 5 1 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 64 144 0 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 39 146 3 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 522 31 194 4 0 1 PRODUCTION 1.26 12-04-2018
xcku115 flva1517 -1 ku_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 522 91 215 4 0 1 PRODUCTION 1.26 12-04-2018

Kintex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcku13p ffve900 -1 kup_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 642 105 242 2 4 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 642 240 399 0 4 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 642 170 244 0 2 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 642 26 61 0 0 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 39 170 3 1 0 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 642 92 372 5 1 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 64 144 0 0 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 39 146 3 0 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 642 31 194 4 0 1 PRODUCTION 1.23 03-18-2019
xcku13p ffve900 -1 kup_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 642 90 215 4 0 1 PRODUCTION 1.23 03-18-2019

Virtex-7

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xc7vx690t ffg1157 -1 v7_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 456 110 242 2 4 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 456 253 399 0 4 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 456 168 244 0 2 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 456 26 61 0 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 40 170 3 1 0 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 456 88 372 5 1 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 65 144 0 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 456 40 146 3 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 456 32 194 4 0 1 PRODUCTION 1.11 2014-09-11
xc7vx690t ffg1157 -1 v7_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 456 91 215 4 0 1 PRODUCTION 1.11 2014-09-11

Virtex UltraScale

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu160 flgb2104 -1 vu_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 522 105 242 2 4 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 522 242 399 0 4 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 522 170 244 0 2 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 522 25 61 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 39 170 3 1 0 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 522 93 372 5 1 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 64 144 0 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 522 39 146 3 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 522 31 194 4 0 1 PRODUCTION 1.27 12-04-2018
xcvu160 flgb2104 -1 vu_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 522 91 215 4 0 1 PRODUCTION 1.27 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -1 vup_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 642 105 242 2 4 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 642 242 399 0 4 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 642 170 244 0 2 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 642 25 61 0 0 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 39 170 3 1 0 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 642 93 372 5 1 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 65 144 0 0 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 39 146 3 0 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 642 31 194 4 0 1 PRODUCTION 1.23 03-18-2019
xcvu9p flgb2104 -1 vup_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 642 90 215 4 0 1 PRODUCTION 1.23 03-18-2019

Zynq UltraScale+

Part Information Configuration Parameters Performance and Resource Utilization
Device Package Speed Grade Configuration Name
PartsPresent
Channels
Mode_of_Operation
Modulus
Parameter_Entry
Noise_Shaping
Phase_Width
Output_Width
Phase_Increment
Resync
Phase_offset
Optimization_Goal
DSP48_Use
OUTPUT_FORM
PINC1
Clock Input Fmax (MHz) LUTs FFs DSP48s 36k BRAMs 18k BRAMs Speedfile Status
xczu9eg ffvb1156 -1 zup_1_large Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Fixed false Fixed Speed Maximal Twos_Complement aclk 642 104 242 2 4 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_large_resync Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Phase_Dithering 30 17 Streaming true Fixed Speed Minimal Twos_Complement aclk 642 242 399 0 4 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_ras_fact4 Phase_Generator_and_SIN_COS_LUT 1 Rasterized 12444 Hardware_Parameters None 14 16 Programmable false None Speed Minimal Twos_Complement aclk 642 170 244 0 2 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_ras_prime Phase_Generator_and_SIN_COS_LUT 1 Rasterized 241 Hardware_Parameters None 8 16 Programmable false None Speed Minimal Twos_Complement aclk 642 26 61 0 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_sfdr110 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 12 20 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 39 170 3 1 0 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_sfdr140 Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters Taylor_Series_Corrected 25 25 Programmable false None Speed Minimal Twos_Complement aclk 642 92 372 5 1 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_sfdr70_of Phase_Generator_and_SIN_COS_LUT 1 Standard Hardware_Parameters None 12 12 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 64 144 0 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_sfdr84 Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 12 14 Programmable false None Speed Minimal Twos_Complement 101000010001 aclk 642 39 146 3 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_taylora Phase_Generator_and_SIN_COS_LUT 1 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 642 31 194 4 0 1 PRODUCTION 1.25 05-09-2019
xczu9eg ffvb1156 -1 zup_1_taylorb Phase_Generator_and_SIN_COS_LUT 16 Standard 9 Hardware_Parameters Taylor_Series_Corrected 20 18 Programmable false None Speed Maximal Twos_Complement aclk 642 90 215 4 0 1 PRODUCTION 1.25 05-09-2019

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