Resource Utilization for 10G/25G Ethernet Subsystem v3.1

Vivado Design Suite Release 2019.2

Interpreting the results

This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core. Consult the product guide for this IP core for a list of GUI parameter and user parameter mappings.

Data is provided for the following device families:

Virtex UltraScale

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
CORE
LINE_RATE
NUM_OF_CORES
DATA_PATH_INTERFACE
ENABLE_PREEMPTION
BASE_R_KR
INCLUDE_FEC_LOGIC
INCLUDE_RSFEC_LOGIC
INCLUDE_AUTO_NEG_LT_LOGIC
INCLUDE_AXI4_INTERFACE
INCLUDE_USER_FIFO
ENABLE_TX_FLOW_CONTROL_LOGIC
ENABLE_RX_FLOW_CONTROL_LOGIC
ENABLE_TIME_STAMPING
PTP_OPERATION_MODE
ENABLE_PIPELINE_REG
RESOURCE_PARAM
LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu095 ffva2104 -2 MAC_KR_10G_FLOWCONTROL Ethernet MAC+PCS/PMA 64-bit 10 1 AXI Stream BASE-KR 0 0 1 1 1 4241 3967 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_1588_10G_1step Ethernet MAC+PCS/PMA 64-bit 10 1 AXI Stream BASE-KR 0 0 1 1 0 1 3945 3895 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_1588_1step Ethernet MAC+PCS/PMA 64-bit 25 1 AXI Stream BASE-KR 0 0 1 1 0 1 4010 3893 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_1588_2step Ethernet MAC+PCS/PMA 64-bit 10 1 AXI Stream BASE-KR 0 0 1 2 0 1 4114 4076 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_25G Ethernet MAC+PCS/PMA 64-bit 25 1 AXI Stream BASE-KR 0 None 0 0 1 4269 4079 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_25G_KRFEC Ethernet MAC+PCS/PMA 64-bit 25 1 AXI Stream BASE-KR 1 None 0 0 1 7268 5832 0 1 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_ANLT Ethernet MAC+PCS/PMA 64-bit 25 1 AXI Stream BASE-KR 0 Include AN/LT Logic 0 0 1 8118 6552 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_ANLT_FEC Ethernet MAC+PCS/PMA 64-bit 25 1 AXI Stream BASE-KR 1 Include AN/LT Logic 0 0 1 11129 8312 0 1 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_ANLT_Pipleline Ethernet MAC+PCS/PMA 64-bit 25 1 AXI Stream BASE-KR 0 Include AN/LT Logic 0 1 1 8250 6419 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_AXIC_Pipleline Ethernet MAC+PCS/PMA 64-bit 25 1 AXI Stream BASE-KR 0 None 1 1 1 9533 21864 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_KRFEC_10G Ethernet MAC+PCS/PMA 64-bit 10 1 BASE-KR 1 None 1 1 1 11987 24333 0 2 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_KR_RSFEC Ethernet MAC+PCS/PMA 64-bit 25 1 AXI Stream BASE-KR 0 1 0 0 1 14088 12164 0 0 4 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_LL_10G Ethernet MAC+PCS/PMA 64-bit 10 1 AXI Stream BASE-R 0 0 0 1 3862 3409 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_LL_25G Ethernet MAC+PCS/PMA 64-bit 25 1 AXI Stream BASE-R 0 0 0 0 1 3973 3415 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_LL_32bit Ethernet MAC+PCS/PMA 32-bit 10 1 2089 1413 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 MAC_TSN_10G_UltraScale Ethernet MAC+PCS/PMA 64-bit 10 1 1 0 6243 5422 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 PCS_ANLT_Pipleline Ethernet PCS/PMA 64-bit 25 1 BASE-KR 0 Include AN/LT Logic 0 1 1 6089 5352 0 0 0 PRODUCTION 1.26 12-04-2018
xcvu095 ffva2104 -2 PCS_KR_RSFEC Ethernet PCS/PMA 64-bit 25 1 BASE-KR 0 1 0 0 1 11934 11115 0 0 4 PRODUCTION 1.26 12-04-2018

Virtex UltraScale+

Part Information Configuration Parameters Resource Utilization
Device Package Speed Grade Configuration Name
CORE
LINE_RATE
NUM_OF_CORES
DATA_PATH_INTERFACE
ENABLE_PREEMPTION
BASE_R_KR
INCLUDE_FEC_LOGIC
INCLUDE_RSFEC_LOGIC
INCLUDE_AUTO_NEG_LT_LOGIC
INCLUDE_AXI4_INTERFACE
INCLUDE_USER_FIFO
ENABLE_TX_FLOW_CONTROL_LOGIC
ENABLE_RX_FLOW_CONTROL_LOGIC
ENABLE_TIME_STAMPING
PTP_OPERATION_MODE
ENABLE_PIPELINE_REG
RESOURCE_PARAM
LUTs FFs DSPs 36k BRAMs 18k BRAMs Speedfile Status
xcvu9p flgb2104 -2 MAC_TSN_10G_UltraScalePlus Ethernet MAC+PCS/PMA 64-bit 10 1 1 0 6249 5437 0 0 0 PRODUCTION 1.26 08-13-2019
xcvu9p flgb2104 -2 MAC_TSN_25G_UltraScalePlus Ethernet MAC+PCS/PMA 64-bit 25 1 1 0 6310 5448 0 0 0 PRODUCTION 1.26 08-13-2019

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