This course provides professors with an introduction to FPGA-based Digital Signal Processing (DSP) design using the Mathworks MATLAB®/Simulink® software and Xilinx System Generator for DSP tools.
Who should attend?
Professors who are new to FPGA-based DSP design.
Digital design experience
Basic HDL knowledge (VHDL or Verilog)
Basic experience with ISE® Foundation™ software
Understanding of fundamental DSP concepts
After completing this workshop, you will be able to:
Understand why FPGAs lend to high-performance DSP design
Understand the basics of Simulink
Identify useful blocks in the System Generator blockset
Model and simulate a System Generator design in Simulink
Understand the hardware impact of various parameter settings
Understand the mechanisms for control
Understand the underlying clocking for multirate systems
FPGAs for DSP
Introduction to System Generator for DSP
Lab 1: Using Simulink
Gain an introduction to Simulink through the simulation of a sine wave, changing the sample rate to analyze the output. Implement an hierarchical design via the creation of a simple filter.
Basic Xilinx Design Capture
Lab 2: Getting Started with Xilinx System Generator
Model a 12x8 MAC using blocks from the Xilinx blockset and simulate it in Simulink. The MAC will be used in a future lab for creating a MAC-based FIR filter.
Lab 3: Signal Routing
Model and simulate logic for padding and un-padding data written to/read from FPGA block memory. This logic will be used in a future lab for creating a MAC-based FIR filter.
Implementing System Control
Lab 4: Implementing System Control
Create an address generator using basic Xilinx blocks and the m-code block. The address generator will be used in a future lab for creating a MAC-based FIR filter.
Lab 5: Designing a MAC FIR
Using elements from the previous labs, model a MAC-based FIR filter and simulate it in Simulink. Test the filter in hardware via hardware-in-the-loop.
Lab 6: Designing a FIR Filter
Generate the coefficients for a band-pass filter using the Filter Design and Analysis (FDA) Tool. Model the bandpass filter using the Xilinx DA FIR and simulate it using white noise input. Test the filter in hardware via hardware-in-the-loop.