We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!



The Xilinx University Program (XUP) enables academics to introduce and use Xilinx technologies in their curriculum and research. XUP collaborates with application expert academics to develop and deliver top-quality teaching materials. XUP also develops in-house workshop materials, teaching users how to use the tools and technologies in the most efficient ways. These workshop materials are accessible to academics to use in classes in their original forms and/or extend with additional material. XUP also gets actively involved in research projects where Xilinx FPGA technologies are utilized.

  • FPGAs are ideal for teaching, projects and research across a whole range of disciplines
  • They are the only reprogrammable, digital platforms which combine:
    • Logic design
    • Micro-processing and computer architecture
    • Digital Signal Processing (DSP)
    • Multi-Gbps communications
  • FPGAs reinforce fundamental principles with practical skills that are important to industry
  • FPGAs provide flexibility which allows new concepts to be quickly verified

  • Xilinx design software
  • Xilinx Intellectual Property (IP) cores
  • FPGA development systems
  • Professor workshops
  • Teaching material
  • Online technical support



XUP has developed number of workshops using Vivado Design suite. These workshops are typically two days long. All workshop materials are in English and consist of presentation slides and lab documents.  

Professors can freely re-use the presentation material in their classroom for teaching purpose. There is no restriction to add, modify or delete the slides giving professors complete control and flexibility to incorporate the material according to the course objectives.

The lab source files are available and can be given to the students to carry out the labs.  Lab solutions are only available to the professors.  They should not be given to students.

Vivado-based Workshops

ISE-based Workshops

Course Materials

XUP Developed Teaching Material

Vivado-Based Digital Design using IPI

Vivado-Based Digital Design using HDL

ISE-Based Digital Design using HDL

Teaching Material Developed at Other Institutions

Coming Soon!

Software & Tools

Boards & Kits

XUP Supported Boards
XUP supports an expanded range of hardware development systems using Xilinx technology to complement the classroom theoretical concepts with hands-on learning in the laboratory.


Vivado Design Suite: System Edition
An integrated software solution supporting the combined methodologies of logic/connectivity, embedded, and DSP design. Available for faculty and researchers.

ISE Design Suite: System Edition
An integrated software solution supporting the combined methodologies of logic/connectivity, embedded, and DSP design. Available for faculty and researchers.

Partial Reconfiguration
Partial Reconfiguration is available as a product within ISE Design Suite, however, requires special licensing to enable this feature. This feature is available to professors and researchers who meet certain criteria. Learn more on requirements and procedure in obtaining license>>

High-Level Synthesis
High-Level Synthesis capability is provided through Vivado High-Level Synthesis. This feature is available as part of the Vivado Design Suite System Edition allowing to target 7-Series and Zynq programmable families. Minimum of ISE Design Suite and a separate feature are required for a complete design flow targeting V6, S6, V5, V4, S3x and V2P. Professors and researchers who want to use this feature targeting the V6, S6, V5, V4, S3x, and V2P families may fill out the donation request form by clicking on the appropriate link in the Quick Links section on the right.

SDAccel Development Environment
The SDAccel™ development environment for OpenCL™, C, and C++, enables up to 25X better performance/watt for data center application acceleration leveraging FPGAs. SDAccel, member of the SDx™ family, combines the industry’s first architecturally optimizing compiler supporting any combination of OpenCL, C, and C++ kernels, along with libraries, development boards and the first complete CPU/GPU like development and run-time experience for FPGAs.

SDSoC Development Environment
The SDSoC™ development environment provides a familiar embedded C/C++ application development experience including an easy to use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq® SoC and MPSoC deployment. Complete with the industry's first C/C++ full-system optimizing compiler, SDSoC delivers system level profiling, automated software acceleration in programmable logic, automated system connectivity generation, and libraries to speed programming. It also enables end user and third party platform developers to rapidly define, integrate, and verify system level solutions and enable their end customers with a customized programming environment.

Intellectual Property Cores

Access IP
A robust catalog of base-level cores to address the general needs of FPGA designers as well as powerful domain and market specific cores to address DSP, embedded, and connectivity designs.


Technical Support

Most Recent Answers Browser
Search for latest, device-specific, or application-specific answer records.

Application Notes
Search for all or area specific application notes

Technical Documentation
Obtain technical documentation on devices, boards, etc.

Service Portal
Web case support is available to professors and researchers in a limited manner. Create a web case to obtain technical support.

General Support

Donation Program
XUP supports faculty through software donation of Vivado Design Suite: System Edition to start a new or enhance an existing course or research project.

General XUP Program information
Send an e-mail requesting information regarding XUP.

Software Licensing
Use our Online Support form for help getting routed to the appropriate customer service team.