Virtualization is a key part of real-time and safety-critical systems, including industrial and automotive. Embedded hypervisors can statically partition the hardware resources available on the platform, and fully dedicate physical CPUs to software domains to minimize IRQ latency. This way, a real-time OS can run alongside larger OSes without being affected by them.
In reality, even with best-in-class hypervisors, real-time deadlines can still be missed due to the presence of a shared L2 cache across the multiple CPU cores. An application on one CPU core can affect the performance of another application in a different virtual machine by causing cache interference.
The solution is cache coloring. This presentation will introduce the new Xen feature to achieve deterministic latency on Cortex-A systems with a shared L2 cache. Cache coloring enables memory allocations with entirely dedicated cache line entries to avoid any cache interference. The presentation will show how to configure a cache coloring Xen deployment and will demonstrate the benefits of the technology with detailed latency measurements and live demos based on the Xilinx Zynq UltraScale+ MPSoC.