UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 61200

2014.2 Vivado Partial Reconfig - How do I manually control the placement of the PartPins in Partial Reconfiguration flow?

描述

How do I manually control the placement of the PartPins in Partial Reconfiguration flow?

解决方案

Poor placement does affect the design (timing and/or routing issues) in PR flow, you can manually control the placement of PartPins using HD.PARTPIN_RANGE. 

It is possible to put a custom range on the SERDES pins only for the right side of the RP Pblock. 

For example:
 
set_property HD.PARTPIN_RANGE SLICE_Xx0Yy0:SLICE_Xx1Yy1 [get_pins <RP_cellName>/<serdes_pins>]

The x0y0/x1y1 would be coordinates along the right side of the Pblock.

The PartPin range does need to be kept with the Pblock range.
AR# 61200
日期 06/20/2014
状态 Active
Type 综合文章
Tools
  • Vivado Design Suite - 2014.2
的页面