New in AMD Vitis™ Software Platform

Enhanced DSP Library Functions for AMD Versal AI Core Series​

• Time division multiplexed (TDM) FIR filter functions for SSR > 1​​
• FFT with 32-bit twiddle ​​
• Mixed-Radix 3 & Mixed-Radix 5 FFTs​​
• Kronecker Matrix Product​​
• Householder-based QRD solver for improved stability​​
• DFT for SSR > 1​​

New DSP library functions for AMD Versal AI Edge Series with AIE-ML​​

• General Matrix Vector (GEMV) with SSR support ​​
• General Matrix Multiply (GEMM) with SSR support ​​​

AIE API Enhancements​​

• Support Radix-3/Radix-5 FFTs 

AI Engine Simulator Enhancements

• Cycle approximate simulation capabilities for AI Engine designs with PL, without the need for CIPS (Control, Interfaces, and Processing System IP Core).
• Vitis analyzer support for hardware emulation with 3rd party simulators such as VCS, Questa, Xcelium,and Riviera

• Export tables from Vitis analyzer to CSV format

• New DSP functions supported for AIE and AIE-ML within AMD Vitis Model Composer​​
  • Time Division Multiplexed (TDM) FIR Filter functions​​
  • For building polyphase channelizers @ 1 GSPS and higher throughput​​
  • DFT/IDFT – with SSR support​​
  • Optimized transforms for throughput/latency on small sizes​​
  • FFT/IFFT – with extended support for CINT32-bit twiddle​​
  • Mixed-Radix FFT/IFFT – with AIE-ML support​
• Ease-of-use improvements to Model Composer Hub block​​
• Enhancements to Hardware Validation flow​​
  
• ​​OS and MATLAB® version support added with v 2024.1:​​
  • RHEL 9​​
  • MATLAB R2023a and R2023b

New example designs ​available on Github.

• A new stencil pragma simplifies HLS C++ code for image and video filters​

• New library function wizards tap into the AMD Vitis libraries github repo​

  • Create “Solver” and “Vision” (OpenCV compatible) IPs for AMD Vivado design tool​
  • Run the available library examples​

• Pragma for memory interface (ap_memory) can now bundle ports for AMD Vivado IP Integrator​

• New HLS component comparison displays side-by-side metrics for 2 or more components​

• Support for user-provider RTL code to replace a C++ function (black-box flow)​

• Code Analyzer can now disaggregate C++ struct members to fine-tune performance analysis​

• New user control for HLS global FSM encoding and selection of safe state​

• Access to Clang sanitizers during C-Simulation to perform address and initialization checks 

New DSP library functions for AI Engines​

• Mixed Radix FFT​
• Discrete Fourier Transform (DFT)
• General Matrix-Vector Multiply (GEMV) ​

​New API support for DSP functions

• FFT IP with cint32 twiddle data types 
• Support for cint16 for Radix-4 FFT APIs 
• Vectorized "fix2flt" and "flt2fix" implemented in API ​

New API support for AIE-ML

• APIs now support int32/cint32 data types in sliding_mul() function
• APIs now support <float> data types in sliding_mul() function
• All AIE API routines required to support sparse matrix multiplication are provided

• AIE compiler can now support 2D and 3D arrays as inputs or outputs
• Vitis Analyzer now generates guidance report to adjust FIFO size
• New support for multi-threaded simulator kernel and value change dump (VCD) analyzer speedup
• External interfacing with MATLAB® environment & Python traffic generators
• Enhanced AXI Stream model with support for empty/wait cycles in PLIO alignment
• Enhanced Design Rule Checking 

• AI Engine trace offload via high-speed debug ​
• NoC and hard DDRMC profiling support in the Vitis environment
• Vitis tool now supports AIE-ML trace for VEK280 and Alveo™ V70 AI inference accelerator card​​

• AI Engine block updates
• Support for importing AIE-ML graphs as blocks into Vitis Model Composer
• New DSPlib functions for AIE and AIE-ML implementation in Vitis Model Composer
• Plotting of AIE simulator output for internal signals in the Simulink® tool
• HLS Kernel block updates
• Automatic test bench generation
• Expanded data type support for HLS Kernel blocks
• Integration of Vitis Model Composer and Vitis tool
• Generation of .xo and libadf.a files directly from Vitis Model Composer
  
• Other enhancements
• MATLAB® tool version support: R2021a, R2021b Update 6, R2022a Update 6, R2022b
• Additional topologies supported for the hardware validation flow
• New example collaterals available from GitHub

•  New Vitis Unified IDE for HLS components
• New Vitis HLS license requirements
• New code analyzer feature for obtaining performance estimations before running C synthesis
• Enhancements to AXI interface:
  • Support for HLS AXI Stream side-channels
  • Support for user-configurable AXI master caching
• Other enhancements:
  • New code complexity report to enable identifying design size issues during C synthesis
• Compile time improvements: Average compile time improvement of 20% in 2023.2 compared to 2023.1​¹

DSP Library - FIR Filters​

• Enhanced Fractional Resampler FIR, Single Rate FIR, Half Band FIR, and Rate Change FIR to support coefficient bit widths to be larger than data bit widths​
• Fractional Resampler FIR also supports SSR operation using multiple AIE tiles and incorporates coefficient reload feature​

Solver Library​

• Enhanced API performance with high-performance streaming designs (~300 tiles) ​
• QR and Cholesky Decomposition support for 4D data mover functions to help read or write data from AIE array​s

• AIE compiler can now support 2D and 3D arrays as inputs or outputs in addition to 1D.​
• AIE compiler supports graph-within-graph constructs (subgraphs) and conditional port constructs.​
• New AIE CINT-to-CFLOAT data conversion ​APIs.

• AIE status reporting enhancement to generate a file that includes information about tiles, events, and additional registers on AIE-ML and AIE tiles in the design.​
• Offloading of AIE event trace over high-speed differential pairs (HSDPs) instead of storing it in memory on Versal devices.​
• NoC and hard DDR MC profiling support in the Vitis environment.​
• AIE windowed event trace for inspecting a specific part of an application.​

• Guidance with FIFO sizing to avoid deadlocks.​
• Ability to select nodes that are reported by the AIE simulator to reduce the size of the simulator VCD file and speed up simulation.​
• AIE simulator now generates a report (that can be viewed in the Vitis analyzer) that shows which AIE has memory access violations and how these correspond to lines in the graph C code.​
• Trace view data visualization now supports the AIE-ML array as well.​

• New data type support for FIR filter configurations that target Versal AI Engines
• Two new floating-point functions optimized for DSP58s in Versal adaptive SoCs
• Faster response time for all Vitis Model Composer library functions targeting Versal AI Engines
• Other enhancements:
  • Enhancements to HLS kernel blocks
  • Enhancements to the Vitis Model Composer Hub
  • Support for MATLAB tool versions R2021a, R2021b, R2022a

•  Performance improvements²: Average latency improvements of 5.2% in 2023.1 compared to 2022.2
• Easy way to download, view, and instantiate L1 libraries functions in the Vitis HLS tool
• Enhanced support for AXI transactions and burst reporting within the Vitis HLS tool

DSP library functions

• Super sample rate (SSR) FIR filter implementation on AI Engine now supports coefficient reload feature and dynamic point size 
• Added FFT windowing element to the FFT function that targets the AI Engine array

Solver library functions 

• Quadrature rotation (QR) decomposition
• Cholesky decomposition

Vision library functions

• Four new video functions targeting the AI Engine array

Ultrasound library functions

• Various functions to help build medical ultrasound designs

• Ability to add constraints to control relative placement of kernels in the AI Engine array  - this allows users to get higher performance and better utilization
• Improved modeling of AIE deadlock conditions in x86 simulator
• New AIE API added - Radix 3/5 FFT  and Matrix ‘x’ Vector APIs added

• Generation of AI Engine profiling reports in HW Emulation
• Deadlock detection using XSDB (AMD System Debugger) for both AI Engine and PL-based designs
• Xilinx Runtime (XRT) controlled continuous offloading of AI Engine event trace over PLIO

• Supports PS application on x86 host machine for SW emulation
• Allows SystemC functional models for HW emulation instead of RTL
• Allows users to simulate the AI Engine kernel with a simple RTL test bench or Python script-based traffic generator
• AI Engine status can be analyzed during HW emulation with the Vitis™ analyzer

Vitis environment 2022.2 new simulation options: Processor system x86 simulation and AI Engine x86 simulation: Programmable logic simulation can be performed using the x86 simulator.

• Features for Versal AI Engine Design
• Ability to add graph constraints to AI Engine DSP library blocks designs – better utilization and performance
• New capability for cycle approximate simulation for AI Engine designs
• AI Engine Graph Import block automatically detects Run Time Parameter (RTP) ports
• Enhancements and additions to the DSP Library blocks
• General Features
• Hardware validation flow supported for heterogenous system designs that use PL and AIE array
• Vitis Model Composer Hub block updated to support heterogenous design
  • Automatic detection of valid AI Engine, HDL, and HLS subsystems
• Hardware validation flow enhanced for HDL only designs and HDL → AI Engine → HDL designs for Versal platforms

• Improved 'task level parralellism' coding style support ​
  • Enables faster C simulation and better QoR​
• Additional performance and timing enhancements​​​
  • Improved burst inference ​
  • Automatic inference of Unroll, Pipeline, Array_Partition, and inline pragmas for better performance​
  • Improved timing accuracy resulting in better timing closure at higher frequencies​​
• Other features​​​
  • Analysis and debug: printf inserted in C-code now supported even after synthesis in the RTL​
  • Ease of use: new performance pragma to automatically achieve a given transaction interval​
  • HLS::stream interfaces now supported by FFT and FIR IP​​​​

• new Genomics Accelerator Library Added (L1&L2 and L3
• Graph Library, L3 enhancements for performance
• Vitis Database Library, GQE Multi-Functional Kernel
• New functions added in Vision Library
• New functions in Vitis AIE Vision Library additions/enhancements
• Vitis AIE DSP library, FIR resampler supersedes FIR fractional interpolator
• Vitis Codec Library new APIs, API jxlEnc, API ‘leptonEnc’, API ‘resize’, API ‘WebpEnc’

Vitis Data Compression Library

• ZLIB Compress Improvement, Customized Octa-Core compression for 8KB solution
• ZLIB Decompression Improvement, Customized IP for 8KB file size

• Platform Capability Query Improvement
• HBM Easy-of-Use Improvement, Ability to choose a specific S_AXI entry point to the HMSS for a kernel M_AXI, RAMA insertion supported from the configuration files

Vitis AI Engine Compiler

• AI Engine Automated Stall/Deadlock Detection & Analysis in Hardware
• Analyzing the Automated Status Output
• Analyzing the Automated Status Output – Buffers
• Analyzing the Manual Status Output in Hardware
• Analyzing the Manual Status Output
• AI Engine Event Trace Enhancements
• External traffic generators AIEsim
• AI Engine Profiling Improvements on HW
• AI Engine support for Broadcast windows
• Vitis AI Engine Compiler Enhanced Graph Programming Model
• Vitis AI Engine Compiler - PLIO/GMIO in ADF Graphs

Vitis HLS

• Analysis Enhancements, New Timeline Trace Viewer
• Coding Style Enhancements, Array Partition support for Stream of Blocks type
• Pragma Abstraction, New Performance Pragma (and directive)
• Vitis Core “one liner”, Vitis HLS - New Timeline Trace Viewer,  new PERFORMANCE pragma,  Stream of Blocks support windows
• New Viewer introduced
  • Shows the runtime profile of all surviving functions in your design - i.e., those that get converted into modules
  • Especially useful to see the behavior of dataflow regions after Co-simulation
  • Native to Vitis HLS - No need to launch the xsim waveform viewer anymore (external tool)

Vitis Analyzer

• Vitis Analyzer Improvement, Save/Restore Timeline Customization
• Reporting Enhancement, report_qor_assessment, xclbin Clocking Information, Vivado Automation Summary
• Profiling Enhancement, New PL profiling infrastructure enabled, Multiple trace_memory options can be added to insert multiple memory monitors (HW Only), Sample config file for v++ linker to offload trace data for all CUs in SLR0 to DDR0 and same for all CUs in SLR1 to DDR1 

Vitis IDE

• Updated Bootgen GUI for Versal
• Toolchain Update
• XSCT, Support STAPL, Add Linker script generation command
• System Compile Flow, Refer to system compile doc

Vitis Emulation

• Add Software Emulation support for Auto-restart and mailbox support for always running kernels
• Free running kernel doesn’t need while(1) for sw-emu
• Add Software Emulation support for external traffic generator
• Hardware Emulation can use HLS C source code function model for Streaming IP.

• Add API xrt::system for Probing number of devices
• Add API xrt::message for Logging messages
• XRT Native API host code now requires
  -std=c++17 or above
• Add experimental xrt::queue APIs for asynchronous execution of synchronous operations
• xbutil can show AIE FIFO counters that helps to debug AIE deadlock scenarios
• xbutil --legacy option is removed.           
• xclbinutil --info provides clock information for embedded platforms
• xbutil on ARM can load SOM images
• xbtop standalone utility to show linux top like output (replacing legacy xbutil -top)
• XRT Utilities supports auto-completion in Bash with tab key.

• Alveo Platform Updates, Platform Updates for improved stability, Card Management Updates, SC Firmware Update Tool
• Embedded Platform, New VCK190 DFX Platform: xilinx_vck190_base_dfx_202210_1, Embedded Platforms are now installed with Vitis, Vivado adds a new Customizable Example Design: Vitis Platform for MPSoC

• Major overhaul of the Vitis Model Composer hub block for scalability and ease of use
• Hardware validation flow now supports Linux in addition to bare-metal
• "AIE to HDL" and "HDL to AIE" blocks no longer include the HDL gateway blocks
• 2022.1 now ships with a snapshot of the examples for customers who do not have access to the internet. The tool will prompt the user to download a new revision of the examples from GitHub if available
• For ease of use, utility blocks that are not part of code generation are now presented with a white background color
• Enhanced and reorganized the library browser for ease of use
• RHEL 8.x support
• MATLAB Support - R2021a and R2021b

Note: Vitis Accelerated Libraries are available as a separate download. They can be downloaded from GitHub or directly from within the Vitis IDE as well.

Note: For vision, just count the number of sub folders in L*/tests, because each API  has multiple tests for different types

Vitis Vision Library

• Programmable Logic (PL)
  
  • End-to-end Mono Image Processing（ISP）with CLAHE TMO
  • RGB-IR along with RGB-IR Image Processing(ISP) pipeline
  • Global Tone Mapping(GTM) along with an ISP pipeline using GTM

Vitis Data Analytics Library

• Vitis Blockchain Solution based on Vitis libraries
  • Out-of-Box Mining solutions for Ethereum
  • Open-Source & easy to use and deploy with Vitis Libs using C++
  • Flexible & Scalable with Vitis Libs
  • Be flexible to mine multiple coins
  • Customize and compile into hardware
  • Highly optimized design
• Adding CSV parser API into library
  • CSV parser could parse comma-seperated value files and generate object stream which could easily be connected with DataFrame APIs

Vitis Graph Library

• New L2 libraries added
• Louvain with renumber
• Renumbering
• The ‘weight’ feature is supported for Cosin Similarity

Vitis Database Library

• GQE start to support asynchronous input / output feature, along with multi-card support.
  • Asynchronous support will allow the FPGA start to process as soon as part of the input data is ready. 
  • Multi-card support allows to identify multiple Alveo cards that suitable for working.

Vitis Data Compression Library

• ZSTD Mult-Core Compression
  • Created new ZSTD multi-core architecture and provided >1GB/s throughput using quad-core.
• ZSTD Decompress optimization
  • ZSTD decompress optimized for performance (increased by 20%) and resource (reduced  < 30%)
• GZIP/ZLIB Stream Core Improvement for IBM
  • Customized Static & Dynamic compress streaming IP (4KB & 8KB)
  • Added functionality to provide compressed size in TUSER port
• GZIP/ZLIB Decompress Improvement for IBM
  • Optimized huffman decoder to reduce latency < 1.5K cycles
  • Reduced resources significantly  from to 6.9K (older > 9K)
  • Added ADLR32 Checksum Functionality
• GZIP System Compiler PoC
  • Created a System Compiler PoC for GZIP Compress solution and benchmarked against OpenCL Host.

Vitis DSP Library

• DSPLib on Github since 2021
• Fast Fourier Transform (FFT/iFFT)
  • Point size increase to 32k (data type dependent)
  • Support for stream API as well as window API.
  • Parallel Power (0-4)
    • Allows higher throughput and extends range of supported point sizes

• FIR Filters
  • Initial Stream support for Single Rate asymmetric / symmetric FIR

• DDS/Mixer
  • New library unit  in 2021.2

Vitis Security Library

• KECCAK-256 (hash function) and CRC32C (checksum function) are released

Vitis Utilities Library

• Two Data-Mover implementation are added for debugging hw issue.
  • LoadDdrToStreamWithCounter: For loading data from PL’s DDR to AI Engine through AXI stream and recording the data count sending to AI Engine.
  • StoreStreamToMasterWithCounter: For receiving data from AI Engine through AXI stream and saving them to PL’s DDR, as well as recording the data count sending to DDR.

Xilinx Runtime Library (XRT): 

• XRT API
  • The XRT native API supports user managed kernel control with xrt::ip
• XRT Utilities
  • The xbutil and xbmgmt tools now becomes default
    • To use the legacy utilities, please use xbutil --legacy or xbmgmt --legacy with legacy sub-commands
  • New utility, xball
    • Apply xbutil or xbmgmt commands to all or a filtered part of the installed data center cards. Check xball --help for details
  • A new command, xbutil configure
    • Allow you to enable, disable, or configure the PCIe Host Memory and PCIe Peer to Peer features. See the XRT documentation for more details
  • All XRT utilities now globally support the --force option to skip user interactive confirmation
• Profiling
  • A profile summary report is generated when any profiling option is enabled.
  • All applicable summary tables and guidance are generated based on the profiling options enabled in the xrt.ini file
  • New data transfer summary table for aggregate information on a memory resource when monitors are added to memory resources in the design
  • New AIE profiling metric sets to count different AIE events including (1) floating point exceptions in AIE, (2) tile execution counts, and (3) stream puts and gets
• Embedded
  • zocl memory manager improvements to support any sptag

Vitis XRT for AI Engine Multiple Process Support

• C and C++ APIs to define access modes for multiple processes to share access to the same AI Engine array and graphs.
  • ¬Protect AI Engine array & graphs from unwanted access.
• Three modes are supported for opening AI Engine array & graphs
  • Exclusive Mode (prevent any other processes to access)
  • Primary Mode (only allow other processes to do nondestructive access)
  • Shared Mode (only do nondestructive access)
• Take into consideration when multiple process support is needed. For example:
  • Prevent others to access AI Engine array(exclusive access)
  • Multiple users to control different graphs separately (multiple application support)
  • One primary user to control graph, and allow others to probe the running status (primary & shared access)

Vitis XRT for AI Engine Support Status

C and C++ APIs

• C version API 
  • For AI Engine array:
    • xrtAIEDeviceOpenExclusive (Exclusive mode)
    • xrtAIEDeviceOpen (Primary mode)
    • xrtAIEDeviceOpenShared (Shared mode)
  • For AI Engine graph:
    • xrtGraphOpenExclusive (Exclusive mode)
    • xrtGraphOpen (Primary mode)
    • xrtGraphOpenShared (Shared mode)
• C++ version API 
  • xrt::aie::device class support access mode in constructor
    • enum class access_mode : uint8_t { exclusive = 0, primary = 1, shared = 2 };
  • xrt::graph class support access mode in constructor
    • enum class access_mode : uint8_t { exclusive = 0, primary = 1, shared = 2, none = 3 };

• Access latest Vitis Target Platforms for Alveo Cards and refer to the Getting Started section of the Accelerator Card.
• Download Vitis and refer to the Alveo Packages section

AI Engine DSP Library – New Blocks

• AIE DDS
• AIE Mixer

Parallel Compilation

• Reduced times vs. 2021.1 (As an example, the following numbers are for the 200 MHz TX Chain):
• Time to compile and simulate reduced by factor of 3
• Compilation times reduced by a factor of 7
• Dead time after simulation reduced from 25s to ~0s

Constraint Editor Enhancement

• 2021.2 Improved Navigation

To Fixed Size Improvements

To Variable Size Block  Improvements

Enhanced Functional Co-simulation Capabilities

• Export Matlab data for AI Engine input – xmcVitisWrite
• Import AI Engine Data into Matlab – xmcVitisRead
• Import AI Engine Data into Matlab - xmcVitisRead

Others

• Import an AI Engine or HLS Kernel block with no input (Source block)
• New Data Type Support
  • the Simulink native int64 and uint64 for AI Engine development instead of AMD data types, x_sfix64 and x_ufix64.
  • accfloat and caccfloat for AI Engine Development
• Support for Ubuntu 20.04
• Support for MATALB 20a, 20b, 21a (No support for MATLAB 21b)
• Addition of new examples
  • Dual stream SSR filter example with 64 kernels
  • Pseudo inverse(64x32) – commslib example.
• Use xmcLibraryPath command to point to a custom DSPLib location.
• Many more enhancements and bug fixes

Note: Vitis Accelerated Libraries are available as a separate download. They can be downloaded from GitHub or directly from within the Vitis IDE as well.

• Stable native XRT API, with C++ APIs for AIE graph control and execution, Software Emulation and tracing support.
• XRT provides new helper APIs to help users to move from OpenCL API to XRT native API in $XILINX_XRT/include/CL/cl2xrt.hpp.
• XRT New API xrt::device.get_info() can extract device properties
• Greatly improved next generation xbutil and xbmgmt utilities are now the default.
• xbutil can report power status
• xbmgmt can support runtime clk scale and setup user power threshold to protect board and server.
• sysfs, xbmgmt and xbutil can report MAC address of Alveo board
• KDS scheduler in xocl has been refactored to significantly improve the throughput across hundreds of processes exercising multiple compute units across multiple devices concurrently. For legacy shells you may notice small percentage of throughput degradation. Please see the AR for proper solution.
• XRT driver debug trace support through debugfs /sys/kernel/debug/xclmgmt/ and /sys/kernel/debug/xocl/

Access the latest Vitis Target Platforms for Alveo Accelerator cards at www.xilinx.com/alveo. Please refer to the Getting Started section of the accelerator card you want to deploy your applications on.

Please refer to UG1120 - Alveo Data Center Accelerator Card Platforms User Guide for more details and to keep up-to-date on the latest Vitis Target Platform releases, as they become available.

New Platforms 

• Alveo U200 Gen3x16 XDMA 1RP
  • Name: xilinx_u200_gen3x16_xdma_1_202110_1
  • Features: Slave Bridge, P2P, GT Kernel, DDR Self-Refresh
• Alveo U50 Gen3x16 noDMA 1RP 
  • Name: xilinx_u50_gen3x16_nodma_1_202110_1
  • Features: Slave Bridge, P2P, GT Kernel, Clock Throttling

Vitis Embedded Platforms

• VCK190 Base Platform enables ECC on DDR and LPDDR; constraints become concise.
• MPSoC base platforms increased CMA size to 1536M. All Vitis-AI models can run with this CMA size.
• Embedded platform creation flow gets simplified: Device Tree Generator can automatically generate a ZOCL node; XSCT can generate BIF files. Base platform source files are reduced.

• A comprehensive constraint editor enables users to specify any constraint for AI Engine kernels in Vitis Model Composer. The generated ADF graph will contain these constraints. 
• Addition of AI Engine FFT and IFFT blocks to the library browser. 
• Users now have access to many variations of AI Engine FIR blocks in the library browser. 
• Ability to specify filter coefficients using input ports for FIR filters. 
• Addition of two new utility blocks "RTP Source" and "To Variable Size".
• Enhanced AIE Kernel import block now also supports importing templatized AI Engine functions. 
• Ability to specify AMD platforms for AI Engine designs in the Hub block.
• Through the Hub block, users can relaunch Vitis Analyzer at any time after running AIE Simulation. 
• Users can now plot cycle approximate outputs and see estimated throughput for each output using Simulink Data Inspector. 
• Enhanced usability to import a graph as a block using only the graph header file. 
• Revamping of the progress bar with cancel button
• Usability improvement during importing an AI Engine kernel or simulation of a design when MATLAB working directory and model directory are not the same. 
• New TX Chain 200MHz example. 
• New 2d FFT examples showcasing designs with HLS, HDL, and AI Engine blocks. 

HDL

• Simulation speed enhancement for SSR FIR (more than 10x improvement), and SSR FFT.
• Simulation speed enhancement for memory blocks like RAMs, and FIFOs
• Questa Simulator updated with VHDL 2008 in the Black-box import flow

General

• Vitis Model Composer now contains the functionality of AMD System Generator for DSP.  Users who have been using AMD System Generator for DSP can continue development using Vitis Model Composer.
• MATLAB Support - R2020a, R2020b & R2021a