Unified Extensible Flash Controller

产品描述

The MXIC Flash Host Controller is used to access Flash, including NOR and NAND Flash for high throughput and low pin count applications. The controller operates in one of these modes: I/O Mode, Linear Addressing Mode (Mapping Mode) and DMA Mode. In I/O Mode, software interacts closely with the flash device protocol. The software writes the flash commands and data to the controller using TXD Register. Software reads the RXD register that contains the data received from the flash device. This process is called as Buffer Read Write data transfer. In Linear Addressing Mode, after accepting AXI Burst Read or Write Command, the controller emulates the software to send Read or Write instructions to the flash device. Besides Buffer Read Write data transfer, the controller also supports DMA data transfer. A DMA master engine is included in the controller. The Host Controllers supports SDMA only. With AXI Slave interface, the Host Controller can also be a DMA Slave, which behaves like Linear Addressing Mode besides the flash instructions should be issued by software.


主要特性与优势

  • Data Rate: SDR(S), DDR(D)
  • Flexible I/O: Single Flash in 1-bit, 4-bit, 8-bit interface and Dual Flash in 1-bit, 4-bit, 8-bit stacked interface
  • Programmable bus protocol: SPI, QSPI, OCTA and ONFI
  • 32-bit AXI interface (Master) for DMA transfer
  • 32-bit AXI interface (Slave) for Linear Addressing Mode transfer
  • 32-bit AXI Lite interface (Slave) for I/O Mode transfer

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z014S -1 Vivado 2016.4 Y 4013 5621 2 0 0 0 200
Zynq-7000 Family XC7Z030 -1 Vivado 2016.4 Y 4619 5496 4 0 0 0 200

IP 质量指标

综合信息

数据创建日期 Sep 08, 2020
当前 IP 修订号 003
当前修订日期已发布 Jan 07, 2020
第一版发布日期 Jan 07, 2020

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 1
可否提供参考? Y

交付内容

可供购买的 IP 格式 Source Code
源代码格式 Verilog
是否包含高级模型? N
模型格式 NA
提供集成测试台 Y
集成测试台格式 OVM System Verilog
是否提供代码覆盖率报告? Y
是否提供功能覆盖率报告? Y
是否提供 UCF? XDC
商业评估板是否可用? Y
评估板所用的 FPGA Zynq-7000
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Bare Metal & Linux

实现方案

代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 Instantiation
定制 FPGA 优化技术 source code
所支持的综合软件工具及版本 Vivado Synthesis
是否执行静态时序分析? Y
AXI 接口 AXI4, AXI4-Lite
是否包含 IP-XACT 元数据? Y

验证

是否有可用的文档验证计划? Executable and documented plan
测试方法 Both
断言 Y
收集的覆盖指标 Assertion
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Cadence NC-Sim

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 Zynq-7000
已通过的行业标准合规测试 N
是否提供测试结果? N