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AXI Central DMA Controller


Product Description

The Xilinx LogiCORE™ IP AXI Central Direct Memory Access (CDMA) core is a soft Xilinx Intellectual Property (IP) core for use with the Vivado® Design Suite. The AXI CDMA provides high-bandwidth Direct Memory Access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol. An optional Scatter Gather (SG) feature can be used to offload control and sequencing tasks from the system CPU. Initialization, status, and control registers are accessed through an AXI4-Lite slave interface, suitable for the Xilinx MicroBlaze™ processor.

Key Features and Benefits

  • AXI4 interface for data transfer
  • Independent AXI4-Lite slave interface for register access
  • Independent AXI4 Master interface for optional Scatter/Gather function
  • Optional Data Re-Alignment Engine
  • Register Direct Mode
  • Optional Scatter Gather DMA support
  • Optional Store and Forward support
  • Parameterized Read and Write Address Pipeline depths
  • Fixed-address and incrementing-address burst support

Resource Utilization



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