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    AMD Intellectual Property

AXI Interconnect

发布者: AMD

The AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specifications from Arm®, including the AXI4-Lite control register interface subset.

  • 设计工具支持: Vivado Software
  • 捆绑产品: Vivado Software
  • 许可: End User License Agreement
  • 器件支持: Artix 7, Kintex 7, Kintex UltraScale, Kintex UltraScale+, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Zynq UltraScale+ MPSoC