ChipScope AXI Monitor



The ChipScope™ AXI Monitor core is designed to monitor and debug AXI interfaces. The core allows the probing of any signals going from a peripheral to the AXI interconnect. For example, the user can instantiate a monitor on a MicroBlaze™ instruction or data interface to observe all memory transactions going in and out of the processor.


  • Selectable data samples
  • 具有可选宽度的通用触发器/数据单元
  • Auto-generated CDC file
  • Multiple monitor support in single system through the use of trigger in and trigger out ports
  • Allows multiple match units per trigger group
  • Added functionality for more than one match unit per trigger group
  • Adjustable counter size for triggers
  • Selectable AXI Protocol Check monitoring for the AXI4 Memory Map and AXI4-Lite interface
  • Supports connection to AXI3 Protocol Cores
  • Supports EDK and standard CORE Generator flows




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