A critical component in the majority of DSP systems is the sinusoid generator, commonly called a Direct Digital Synthesizer (DDS) or numerically controlled oscillator (NCO). These DDS functions while simple algorithmically presents numerous difficulties to hardware engineers tasked with implementing the function. For example, it is frequently a challenge to limit the memory consumed for high SFDR requirements and also to reach maximum clock performance in the device. The DDS Compiler eliminates these difficulties and reduces implementation time to the push of a button. Furthermore, the tool provides users with the ability to make implementation trade-offs between XtremeDSP™ slice, Block Memory and Logic in order to achieve the most optimum solution for a given system.
Key Features and Benefits
Phase Generator and SIN/COS Lookup Table can be generated individually or together with optional dither to provide a complete DDS solution.
Rasterized feature eliminates phase noise from phase truncation.
Sine, cosine, or quadrature outputs
Optional per-channel resynchronization of accumulated phase.
Lookup table can be stored in distributed or block RAM
Optional phase dithering spreads the spectral line energy for greater Spurious Free Dynamic Range (SFDR)
Phase Dithering or Taylor series correction options provide high dynamic range signals using minimal FPGA resources
Supports SFDR from 18 dB to 150 dB
Up to 16 independent time-multiplexed channels
Fine frequency resolution using up to 48-bit phase accumulator with DSP slice or FPAGA logic options
3-bit to 26-bit signed output sample precision
For use with Vivado® IP Catalog and Xilinx System Generator for DSP