Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
发布者: AMD
The LogiCORE™ IP HDMI Reference Design implements HDMI digital video interface in AMD FPGAs.
AMD offers HDMI™2.1 IP subsystems and HDMI2.0 IP subsystems. HDMI2.1 Subsystems are designed to HDMI2.1 specification and supports earlier HDMI standards with support for FRL and TMDS modes and throughput up to 48Gbps. HDMI2.0 IP subsystems designed to HDMI2.0 specification and supports earlier standards with up to 18 Gbit/s throughput over TMDS signaling.
HDMI2.1 subsystems support Ultrascale+™ devices.
HDMI2.0 Subsystems supports Versal™ adaptive SoC, UltraScale+, UltraScale™ and 7 Series AMD FPGAs.
To help users in creating video solutions with HDMI interfaces, AMD offers prepackaged subsystems for HDMI receive or HDMI transmit. These subsystems integrate commonly used functions with video interfaces such as video timing generation, AXI bridges and optional HDCP function with HDMI controller and work out of the box. These subsystems need additional HDMI GT controller (HDMI2.1) or Video phy controller (HDMI2.0) for physical layer implementation.
The HDMI subsystems are designed to be compliant with the HDMI 2.0 standard and includes the following features:
The HDMI 2.1 subsystems are designed to be compliant with the HDMI 2.1 standard and includes the following features:
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.