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AR# 14920

Virtex-II Pro RocketIO - How do I ensure that my design will not overflow or underflow the RX (receiver) elastic buffer because of RX/TX clock differences (clock correction)?


How do I ensure that I insert enough IDLE characters to account for clock differences between the RX and TX sides?


The number of clock correction sequences depends on the frequency tolerance of the clocks on the TX and RX sides. The clock used to clock data into the RX elastic buffer is the recovered clock (RXRECCCLK). This is performed internally in the RocketIO block. The RXUSRCLK is used to clock data out of the RX elastic buffer. In defining the frequency tolerance (how far it can be from the specified frequency output) of the oscillators to be delta_F, the following is true:

CC_period = TXUSRCLK_cycles per one extra or missing RX character = 1 / (delta_F_tx + delta_F_rx)

This is the number of TX clock cycles that occur before one extra or one fewer character appears in the RX elastic buffer. To keep the buffer half full, an extra character must be removed (buffer is getting full), or the missing character must be added (buffer is getting empty). This means that you must send one clock correction character (8 or 10 bits) in every CC_period cycles on TXUSRCLK.

For example:

A clock is 100 MHz, with a 5% frequency tolerance, the RX and TX clocks have the same tolerance, and 8b/10b encoding is used.

CC_period = 1/ (.05 + .05) = 10

For this setup, you must insert one removable/repeatable byte (clock correction byte) in every 10 bytes. As clock correction sequences can be up to four bytes, you could send:

- A sequence of 1 byte in every 10 bytes

- A sequence of 2 bytes in every 20 bytes

- A sequence of 3 bytes in every 30 bytes

- A sequence of 4 bytes in every 40 bytes

Without 8b/10b encoding, each byte would be a 10-bit character.

You can then perform a simulation to ensure that the design does not overflow the RX buffer.

To do this, set up a RocketIO Smart (SWIFT) model in serial loopback mode with TXUSRCLK and RXUSRCLK off by the largest margin of error for the two clocks in the actual design. For example, if the oscillator used for the TX and RX has a tolerance of 5%, set the two clocks to be off by 10%. This will cause clock correction to occur in the simulation.

Monitor the RXBUFSTATUS pin to ensure that the incoming serial data stream does not cause the RX buffer to overflow or underflow. If you observe an overflow or underflow condition, have the TX side of your design insert more clock correction characters (which can be removed/repeated in the buffer by the transceiver logic).

Common accuracy and the frequency of clock correction required:

______________________________________Max cycles before correction

Osc Freq___Osc Accuracy__Line Speed___(remove/repeat 1 sequence)

156.25_____100 ppm_______3.125 Gbps____4,999

156.25______50 ppm_______3.125 Gbps____9,999

156.25______20 ppm_______3.125 Gbps____24,999

125.00_____100 ppm_______2.500 Gbps____4,999

125.00______50 ppm_______2.500 Gbps____9,999

125.00______20 ppm_______2.500 Gbps____24,999

62.500_____100 ppm_______1.250 Gbps____4,999

62.500______50 ppm_______1.250 Gbps____9,999

62.500______20 ppm_______1.250 Gbps____24,999

AR# 14920
日期 08/29/2012
状态 Active
Type 综合文章
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