AR# 16519


Packaging - What is coplanarity? Does Xilinx have a max PCB warpage recommendation?


  • In IC packaging parlance, what is "coplanarity"?
  • What is happening when "warpage" is reported on the package?


Coplanarity is defined as a unilateral tolerance zone measured upward from the seating plane. The solder balls are not all aligned with respect to the seating plane and a tolerance for this misalignment is specified.

The industry-standard coplanarity limits are generally 0.2 mm (~8 mils) or 0.25mm (~10 mils) (i.e., the worst-case height from the seating plane to the ball surface is 0.2 mm or 0.25 mm).

Xilinx device packages are well within this limit. Generally, the solder paste layer is made to account for this lack of coplanarity so that all balls appear set in. 

The coplanarity specifications for various packages are included in the package drawings available on and included in the product family Packaging User Guide, under Mechanical Drawings section.

(Look for the "aaa" spec in these drawings. Some have a "ccc" spec instead.)

Warpage (or warping) occurs when the package profile bends or becomes uneven as a result of thermal stress and/or moisture sensitivity. This directly leads to mounting issues. Poor coplanarity might magnify warping issues.

Xilinx does not provide a max warpage specification on the PCB side. It is recommended that customer match our coplanarity specification as closely as possible.

Several issues relating to reflow conditions can cause excess warpage. We recommend that reflow soldering performed for Xilinx packages adhere as closely as possible to the guidelines presented in the Device Packaging User Guide available on

AR# 16519
日期 01/14/2021
状态 Active
Type 综合文章
器件 More Less
People Also Viewed