I ran my design through the tools fine, and then I opened Floorplanner and performed a "FloorPlan -> Replace All with Placement" command. I exported a UCF and ran it through the tools again, expecting the same results. However, an error during MAP indicates that the design is too large for the part:
"ERROR:Pack:18 - The Design is too large for given device and package."
This is the same design that I just ran through, so how can it now be too large?
The problem is with how the tools combine logic. For instance, if you have several inverters in your design, they will usually be combined into a LUT. However, if the LUT that it would normally be combined into has a LOC constraint on it, the current version of tools cannot merge the inverter with it. This in turn causes the INV to use another LUT, increasing the overall size of the design.
This issue is being reviewed, and will be fixed in a future release of the software.