AR# 17924


Synopsys Formality/Verplex Conformal - Verification fails on block RAMs when using a simulation netlist generated by the ISE design tools


MAP will optimize away grounded inputs to the block RAMs. For instance, if the write enable on PORTB is grounded, MAP will leave the DIB inputs unconnected, even if they were connected to ground in the input design. This optimization will cause verification errors in both Formality and Conformal.

netgen -ecn conformal does not ground DIB ports of MODEM_RX_RAM for post-par netlist.

The NGD netlist was grounded properly. Also block RAM was retargeted from RAMB4 to RAMB16.


To resolve these errors, set the option in Formality or Conformal to ground unconnected input ports.

AR# 17924
日期 12/15/2012
状态 Active
Type 综合文章
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