CPLDFit issues a warning message similar to the following:
"WARNING:Cpld:310 - Cannot apply TIMESPEC TS_2002 = FROM:spiclk_i:TO:myoutput because one of the following:
(a) a signal name was not found;
(b) a signal was removed or renamed due to optimization;
(c) there is no path between the FROM node and TO node in the TIMESPEC."
Double check the signal endpoints to ensure that they exist and are not typed incorrectly.
Intermediate nodes may not always be present after implementation because of optimization. Intermediate nodes are often renamed or merged with other logic; Xilinx recommends using only clocked elements or pins as timing constraint endpoints.
Also, ensure that the path that you are constraining is a valid path and is appropriate to the constraint in question. For example, a period timing constraint on a path that does not have a common clock on both endpoints can be a valid path, but an invalid constraint.
For other common CPLD questions, see the CPLD FAQ at: (Xilinx Answer 24167).